Nighttime image dehazing aims to remove the effect of haze on the images captured in nighttime,which however,raises new challenges such as severe color distortion,more complex lighting conditions,and lower contrast.In...Nighttime image dehazing aims to remove the effect of haze on the images captured in nighttime,which however,raises new challenges such as severe color distortion,more complex lighting conditions,and lower contrast.Instead of estimating the transmission map and atmospheric light that are difficult to be accurately acquired in nighttime,we propose a nighttime image dehazing method composed of a color cast removal and a dual path multi-scale fusion algorithm.We first propose a human visual system(HVS)inspired color correction model,which is effective for removing the color deviation on nighttime hazy images.Then,we propose to use dual path strategy that includes an underexposure and a contrast enhancement path for multi-scale fusion,where the weight maps are achieved by selecting appropriate exposed areas under Gaussian pyramids.Extensive experiments demonstrate that the visual effect of the hazy nighttime images in real-world datasets can be significantly improved by our method regarding contrast,color fidelity,and visibility.In addition,our method outperforms the state-of-the-art methods qualitatively and quantitatively.展开更多
A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is signif...A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.展开更多
基金supported by Higher Education Scientific Research Project of Ningxia(NGY2017009)。
文摘Nighttime image dehazing aims to remove the effect of haze on the images captured in nighttime,which however,raises new challenges such as severe color distortion,more complex lighting conditions,and lower contrast.Instead of estimating the transmission map and atmospheric light that are difficult to be accurately acquired in nighttime,we propose a nighttime image dehazing method composed of a color cast removal and a dual path multi-scale fusion algorithm.We first propose a human visual system(HVS)inspired color correction model,which is effective for removing the color deviation on nighttime hazy images.Then,we propose to use dual path strategy that includes an underexposure and a contrast enhancement path for multi-scale fusion,where the weight maps are achieved by selecting appropriate exposed areas under Gaussian pyramids.Extensive experiments demonstrate that the visual effect of the hazy nighttime images in real-world datasets can be significantly improved by our method regarding contrast,color fidelity,and visibility.In addition,our method outperforms the state-of-the-art methods qualitatively and quantitatively.
基金Project supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033)the National High-Tech Program of China(No.2013AA014103)
文摘A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.
