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Collision Avoidance of Cooperative Dual Redundant Manipulators 被引量:5
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作者 战强 何延辉 陈明 《Chinese Journal of Aeronautics》 SCIE EI CAS CSCD 2003年第2期117-122,共6页
Dual redundant manipulators are extremely useful for tasks in dangerous or space environments, but efficient and real time coordinated control is hard to achieve. Collision avoidance between two cooperative manipulat... Dual redundant manipulators are extremely useful for tasks in dangerous or space environments, but efficient and real time coordinated control is hard to achieve. Collision avoidance between two cooperative manipulators is vital to the successful applications of dual redundant manipulators. Although methods based on the distance function have been demonstrated simple and efficient, different collision avoidance points can usually produce completely different results and even failure. The paper discussed the choices of collision avoidance points and proposed a novel method for the choosing of those points. The method is testified by simulation results of two redundant planar manipulators. 展开更多
关键词 collision avoidance dual redundant manipulators distance function cooperative manipulators
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HYBRID REDUNDANCY APPROACH TO INCREASE THE RELIABILITY OF FPGA BASED SPEED CONTROLLER CORE FOR HIGH SPEED TRAIN
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作者 Omid Akbari Galashi Karim Mohammadi Reza Omidi Gosheblagh 《Journal of Electronics(China)》 2014年第3期256-266,共11页
With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger&... With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger's safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a new effective method which is based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy(HDDR) method, the original controller is quadruplicated and correct values are voted through the comparator and error detection unit. We have analyzed the proposed system with Reliability, Availability, Mean time to failure and Security(RAMS) theory in order to evaluate the effectiveness of proposed scheme. Theoretical analysis shows that the Mean Time To Failure(MTTF) of the proposed system is 2.5 times better than the traditional Triple Modular Redundancy(TMR). Furthermore, the fault injection experimental results reveal that the capability of tolerating Single Event Upsets(SEUs) in the proposed method increases up to 7.5 times with respect to a regular speed controller. 展开更多
关键词 Field Programmable Gate Arrays (FPGAs) Hybrid dual Duplex Redundancy (HDDR) Fault tolerant system Reliability High speed railway
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