A Polynomial Prediction Filter Method for Estimating Multisensor Dynamically Varying Biases

The estimation of the sensor measurement biases in a multisensor system is vital for the sensor data fusion. A solution is provided for the estimation of dynamically varying multiple sensor biases without any knowledge of the dynamic bias model parameters. It is shown that the sensor bias pseudomeasurement can be dynamically obtained via a parity vector. This is accomplished by multiplying the sensor uncalibrated measurement equations by a projection matrix so that the measured variable is eliminated from the equations. Once the state equations of the dynamically varying sensor biases are modeled by a polynomial prediction filter, the dynamically varying multisensor biases can be obtained by Kalman filter. Simulation results validate that the proposed method can estimate the constant biases and dynamic biases of multisensors and outperforms the methods reported in literature.

Soil organic carbon dynamics study bias deduced from isotopic fractionation in corn plant

Carbon stable isotope techniques were extensively employed to trace the dynamics of soil organic carbon(SOC)across a land-use change involving a shift to vegetation with different photosynthetic pathways.Based on the isotopic mass balance equation,relative contributions of new versus old SOC,and SOC turnover rate in corn fields were evaluated world-wide.However,most previous research had not analyzed corn debris left in the field,instead using an average corn plant δ^(13)C value or a measured value to calculate the proportion of corn-derived SOC,either of which could bias results.This paper carried out a detailed analysis of isotopic fractionation in corn plants and deduced the maximum possible bias of SOC dynamics study.The results show approximately 3‰ isotopic fractionation from top to bottom of the corn leaf.The ^(13)C enrichment sequence in corn plant was tassel﹥stalk or cob﹥root﹥leaves.Individual parts accounting for the total dry mass of corn returned distinct values.Consequently,the average δ^(13)C value of corn does not represent the actual isotopic composition of corn debris.Furthermore,we deduced that the greater the fractionation in corn plant,the greater the possible bias.To alleviate bias of SOC dynamics study,we suggest two measures:analyze isotopic compositions and proportions of each part of the corn and determine which parts of the corn plant are left in the field and incorporated into SOC.

Preliminary Evaluations of FGOALS-g2 for Decadal Predictions

The Flexible Global Ocean-Atmosphere-Land System model, Grid-point Version 2 （FGOALS-g2） for decadal predictions, is evaluated preliminarily, based on sets of ensemble 10-year hindcasts that it has produced. The results show that the hindcasts were more accurate in decadal variability of SST and surface air temperature （SAT）, particularly in that of Nifio3.4 SST and China regional SAT, than the second sample of the historical runs for 20th-century climate （the control） by the same model. Both the control and the hindcasts represented the global warming well using the same external forcings, but the control overestimated the warming. The hindcasts produced the warming closer to the observations. Performance of FGOALS-g2 in hindcasts benefits from more realistic initial conditions provided by the initialization run and a smaller model bias resulting from the use of a dynamic bias correction scheme newly developed in this study. The initialization consists of a 61-year nudging-based assimilation cycle, which follows on the control run on 01 January 1945 with the incorporation of observation data of upper-ocean temperature and salinity at each integration step in the ocean component model, the LASG IAP Climate System Ocean Model, Version 2 （LICOM2）. The dynamic bias correction is implemented at each step of LICOM2 during the hindcasts to reduce the systematic biases existing in upper-ocean temperature and salinity by incorporating multi-year monthly mean increments produced in the assimilation cycle. The effectiveness of the assimilation cycle and the role of the correction scheme were assessed prior to the hindcasts.

A dynamic-biased dual-loop-feedback CMOS LDO regulator with fast transient response

This paper presents a low-dropout regulator （LDO） for portable applications with dual-loop feedback and a dynamic bias circuit. The dual-loop feedback structure is adopted to reduce the output voltage spike and the response time of the LDO. The dynamic bias circuit enhances the slew rate at the gate of the power transistor. In addition, an adaptive miller compensation technique is employed, from which a single pole system is realized and over a 59~ phase margin is achieved under the full range of the load current. The proposed LDO has been implemented in a 0.6μm CMOS process. From the experimental results, the regulator can operate with a minimum dropout voltage of 200 mV at a maximum 300 mA load and IQ of 113μA. The line regulation and load regulation are improved to 0. l mV/V and 3.4 μV/mA due to the sufficient loop gain provided by the dual feedback loops. Under a full range load current step, the voltage spikes and the recovery time of the proposed LDO is reduced to 97 mV and 0.142 μs respectively.

A 2.5 GS/s 14-bit D/A converter with 8 to 1 MUX

A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.

Effect of collector bias current on the linearity of common-emitter BJT amplifiers

Using a Volterra series, an explicit formula is derived for the connection between input 3rd-order intercept point and collector bias current （IcQ） in a common-emitter bipolar junction transistor amplifier. The analysis indicates that the larger/CQ is, the more linear the amplifier is. Furthermore, this has been verified by experiment. This study also integrates a method called dynamic bias current for expanding the dynamic range of an LNA （low noise amplifier） as an application of the analysis result obtained above. IMR3 （3rd-order intermodulation rate） is applied to evaluate the LNA＇s performance with and without adopting this method in this study.

Design of an LDO with capacitor multiplier

This paper presents a low quiescent current,highly stable low-drop out（LDO） regulator.In order to reduce capacitor value and control frequency response peak,capacitor multipliers are adopted in the compensation circuit with mathematic calculations.The phase margin is adequate when the load current is 0.1 or 150 mA.Fabricated in an XFAB 0.6μm CMOS process,the LDO produces 12.2 mV（0.7%） overshoot voltage while the current changes at 770 mA/100μs with a capacitor load of 10μF.