Comparison of dynamic Bayesian network approaches for online diagnosis of aircraft system

The online diagnosis for aircraft system has always been a difficult problem. This is due to time evolution of system change, uncertainty of sensor measurements, and real-time requirement of diagnostic inference. To address this problem, two dynamic Bayesian network(DBN) approaches are proposed. One approach prunes the DBN of system, and then uses particle filter(PF) for this pruned DBN(PDBN) to perform online diagnosis. The problem is that estimates from a PF tend to have high variance for small sample sets. Using large sample sets is computationally expensive. The other approach compiles the PDBN into a dynamic arithmetic circuit(DAC) using an offline procedure that is applied only once, and then uses this circuit to provide online diagnosis recursively. This approach leads to the most computational consumption in the offline procedure. The experimental results show that the DAC, compared with the PF for PDBN, not only provides more reliable online diagnosis, but also offers much faster inference.

An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits

In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.

基于等效电路模型理解机械应变对电催化反应的作用

电催化的应变工程被认为是提高材料电催化性能最有效的策略之一.然而,目前还缺乏数学模型来深入理解这些有趣的科学现象.本文基于等效电路理论研究了应变对电极反应中法拉第过程的影响.根据基尔霍夫定律,获得了应变影响电极响应电流的数学表达式,研究了法拉第过程逐渐成为电催化反应的主导作用时,由应变导致的响应电流参数的变化趋势和峰值的变化规律,并深入探索电催化反应中不同因素相互作用的复杂机制.

An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

： This paper presents an l 1-bit 22-MS/s 0.6-mW successive approximation register （SAR） analog-to- digital converter （ADC） using SMIC 65-nm low leakage （LL） CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio （SNDR） is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.

Some new results on time-varying Stratonovich and Itô bilinear stochastic systems

The bilinear stochasticity of dynamical systems is attributed to the input–output coupling term,where the input is a random input and the state is the output of dynamical systems.Stochastically influenced bilinear systems are described via bilinear stochastic differential equations.In this paper,first we construct a mathematical method for the closed-form solution to a scalar Stratonovich time-varying bilinear stochastic differential equation driven by a vector random input as well as the Itôcounterpart.Second,the analytic results of the paper are applied to an electrical circuit that assumes the structure of a bilinear stochastic dynamic circuit.The noise analysis of the bilinear dynamic circuit is achieved by deriving the mean and variance equations as well.The theory of this paper hinges on the‘Stratonovich calculus’,conversion of the Stratonovich integral into the Itôintegral and characteristic function of the vector Brownian motion.The results of this paper will be useful for research communities looking for estimation and control of bilinear stochastic differential systems.

A 2.5 GS/s 14-bit D/A converter with 8 to 1 MUX

A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.

A high-precision synchronization circuit for clock distribution

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm2, and the power consumption is 1.64 mW at 500 MHz.