A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event ups...A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.展开更多
目的建立同时定量检测己二酰肼(adipic acid dihydrazide,ADH)和N-(3-二甲基氨基丙基)-N′-乙基碳二亚胺[N-(3-dimethylaminopropyl)-N′-ethylcarbodimide,EDAC]的液相色谱串联质谱(liquid chromatography tandem mass spectrometry,LC...目的建立同时定量检测己二酰肼(adipic acid dihydrazide,ADH)和N-(3-二甲基氨基丙基)-N′-乙基碳二亚胺[N-(3-dimethylaminopropyl)-N′-ethylcarbodimide,EDAC]的液相色谱串联质谱(liquid chromatography tandem mass spectrometry,LC-MS/MS)法,实现多糖蛋白结合物(肺炎球菌结合物、脑膜炎球菌结合物和b型流感嗜血杆菌结合物)中残留ADH和EDAC的定量研究。方法通过检测EDAC在纯水、中性水溶液[(50 mmol/L磷酸缓冲溶液(pH 6.8)、200 mmol/L氯化钠水溶液和疫苗培养基)]及0.1%甲酸(formic acid,FA)水溶液中的稳定性,确定实现EDAC完全转换为EDU的前处理条件。优化了色谱柱种类对ADH、EDU和EDAC的保留,以及质谱条件如产物离子、碰撞电压、Q1和Q3电压等对ADH和EDU定量灵敏度的影响,建立以C18WCX(2.1 mm×150 mm,5μm)为固定相,pH 2~3的0.1%FA-水和0.1%FA-乙腈为流动相的LC-MS/MS方法,实现ADH和EDAC(实际检测对象为EDAC的转换产物EDU)的高灵敏度定量分析。对建立方法的精密度、准确度、线性范围、检出限(LOD)和定量限(LOQ)进行验证。结果ADH在水溶液中较稳定,EDAC自溶解开始即水解为EDU,且难以完全转换,导致EDAC测定困难;在样品和标准品溶液中加入FA,可实现EDAC完全且快速的转换为EDU。ADH、EDU和EDAC在C18色谱柱上保留弱,在色谱柱的死时间附近出峰,无法实现这些化合物与样品基质的分离,而本文所选C18WCX固定相可实现目标化合物的保留且峰形较好。通过前体离子扫描、产物离子扫描,选择目标化合物的前体离子和响应强度较好的产物离子作为MRM的离子对,并用MRM自动优化程序获得目标化合物的最佳Q1、CE和Q3电压值。建立的方法检测的ADH和EDAC含量与峰面积线性关系良好,R2均大于0.999;ADH的LOD为3.96μg/L、LOQ为15.63μg/L,EDAC的LOD为0.58μg/L、LOQ为1.17μg/L,灵敏度较高;精密度(峰面积RSD<2%)及准确度(回收率为90%~105%)较高。结论建立的LC-MS/MS方法实现了多糖蛋白结合疫苗中残留ADH和EDAC(通过测定EDU定量EDAC)的高灵敏度检测,与《中国药典》三部(2015版)方法相比,该方法预处理更简单,自动化程度更高且灵敏度更好,适合于多种多糖蛋白结合物中ADH和EDAC残留的检测。展开更多
An optimization method of error detection and correction(EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementa...An optimization method of error detection and correction(EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.展开更多
基金the National Natural Science Foundation of China(Nos.12035019,11690041,and 11805244).
文摘A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.
文摘An optimization method of error detection and correction(EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.
