With the development of current electronic technology, numerous high-speed data acquisition systems provide a variety of potential benefits. This article describes a high-speed data acquisition system which consists o...With the development of current electronic technology, numerous high-speed data acquisition systems provide a variety of potential benefits. This article describes a high-speed data acquisition system which consists of ECL logic and TTL logic devices, samples and stores data with a 1 GHz clock. This system is accomplished easily and works stably. A performance test of this system has been undertaken and the results show that the effective number of bits （ENOB） is more than 6.5 bits.展开更多
As a key building block of data acquisition systems, power dissipation of the successive approximation register （SAR） ADC determines the total power consumption of the system. In this paper, a low power 12-bit 1 Msp...As a key building block of data acquisition systems, power dissipation of the successive approximation register （SAR） ADC determines the total power consumption of the system. In this paper, a low power 12-bit 1 Msps SAR ADC with an improved switching procedure is presented. Power consumption and area occupation could be significantly reduced by using the proposed switching procedure. Compared to converters that use the conventional switching procedure, the average switching energy could be reduced by about 80% and the total capacitance could be reduced by 50%. A simplified digital control logic is utilized to reduce power dissipation and area occupation of the digital control circuits. Simulation results show that the power dissipated by the proposed digital control circuits could be reduced by about 50% compared to the power dissipated by conventional control circuits. The chip has been processed in a standard 0.35 μm CMOS technology and has a core die area of 1,12 mm2. A signal-to-noise- and-distortion-ratio of 64.2 dB has been measured with a 100 kHz signal input under a wide range variation of temperature from -55 to 150 ℃ The total power consumption of the prototype is only 0.72 mW with a 3.3 V supply voltage.展开更多
文摘With the development of current electronic technology, numerous high-speed data acquisition systems provide a variety of potential benefits. This article describes a high-speed data acquisition system which consists of ECL logic and TTL logic devices, samples and stores data with a 1 GHz clock. This system is accomplished easily and works stably. A performance test of this system has been undertaken and the results show that the effective number of bits （ENOB） is more than 6.5 bits.
基金supported by the National Basic Research Program of China(No.2014CB744600)the National Natural Science Foundation of China(No.61474120)
文摘As a key building block of data acquisition systems, power dissipation of the successive approximation register （SAR） ADC determines the total power consumption of the system. In this paper, a low power 12-bit 1 Msps SAR ADC with an improved switching procedure is presented. Power consumption and area occupation could be significantly reduced by using the proposed switching procedure. Compared to converters that use the conventional switching procedure, the average switching energy could be reduced by about 80% and the total capacitance could be reduced by 50%. A simplified digital control logic is utilized to reduce power dissipation and area occupation of the digital control circuits. Simulation results show that the power dissipated by the proposed digital control circuits could be reduced by about 50% compared to the power dissipated by conventional control circuits. The chip has been processed in a standard 0.35 μm CMOS technology and has a core die area of 1,12 mm2. A signal-to-noise- and-distortion-ratio of 64.2 dB has been measured with a 100 kHz signal input under a wide range variation of temperature from -55 to 150 ℃ The total power consumption of the prototype is only 0.72 mW with a 3.3 V supply voltage.
