Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench

A lateral insulated gate bipolar transistor(LIGBT)based on silicon-on-insulator(SOI)structure is proposed and investigated.This device features a compound dielectric buried layer(CDBL)and an assistant-depletion trench(ADT).The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that,under the same breakdown voltage(BV)condition,allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers.Reducing their numbers helps in fast-switching.Furthermore,the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel.The simulation results show that the BV of the proposed LIGBT is increased by 113%compared with the conventional SOI LIGBT of the same length L_(D).Contrastingly,the length of the drift region of the proposed device(11.2μm)is about one third that of a traditional device(33μm)with the same BV of 141 V.Therefore,the turn-off loss(E_(OFF))of the CDBL SOI LIGBT is decreased by 88.7%compared with a conventional SOI LIGBT when the forward voltage drop(VF)is 1.64 V.Moreover,the short-circuit failure time of the proposed device is 45%longer than that of the conventional SOI LIGBT.Therefor,the proposed CDBL SOI LIGBT exhibits a better V_(F)-E_(OFF)tradeoff and an improved short-circuit robustness.

High-voltage super-junction lateral double-diffused metal-oxide semiconductor with a partial lightly doped pillar

A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.

Novel fast-switching LIGBT with P-buried layer and partial SOI

A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer,the proposed structure generates two new peaks in the surface electric field distribution,which can achieve a smaller device size with a higher breakdown voltage.The smaller size of the device is beneficial to the fast switching.The simulation shows that under the same size,the breakdown voltage of the BPSOI LIGBT is 26%higher than that of the conventional partial-SOI LIGBT(PSOI LIGBT),and 84%higher than the traditional SOI LIGBT.When the forward voltage drop is 2.05 V,the turn-off time of the BPSOI LIGBT is 71%shorter than that of the traditional SOI LIGBT.Therefore,the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT.In addition,the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.

Breakdown voltage analysis of Al_(0.25)Ga_(0.75)N/GaN high electron mobility transistors with partial silicon doping in the AlGaN layer

In this paper,two-dimensional electron gas（2DEG） regions in AlGaN/GaN high electron mobility transistors（HEMTs） are realized by doping partial silicon into the AlGaN layer for the first time.A new electric field peak is introduced along the interface between the AlGaN and GaN buffer by the electric field modulation effect due to partial silicon positive charge.The high electric field near the gate for the complete silicon doping structure is effectively decreased,which makes the surface electric field uniform.The high electric field peak near the drain results from the potential difference between the surface and the depletion regions.Simulated breakdown curves that are the same as the test results are obtained for the first time by introducing an acceptor-like trap into the N-type GaN buffer.The proposed structure with partial silicon doping is better than the structure with complete silicon doping and conventional structures with the electric field plate near the drain.The breakdown voltage is improved from 296 V for the conventional structure to 400 V for the proposed one resulting from the uniform surface electric field.

Low on-resistance high-voltage lateral double-diffused metal oxide semiconductor with a buried improved super-junction layer

A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.

A high voltage Bi-CMOS compatible buffer super-junction LDMOS with an N-type buried layer

A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.

Novel 700 V high-voltage SOI LDMOS structure with folded drift region

A new high-voltage LDMOS with folded drift region （FDR LDMOS） is proposed. The drift region is folded by introducing the interdigital oxide layer in the： Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.