International exchanges on electrostatic protection and standardization

The 6th Electrostatic Protection and Standardization International Conference was held on November 10,2017 in Guizhou Normal University on the themes of＂promoting the discipline construction of electrostatic protection engineering and accelerating the development of electrostatic protection technology and industry＂.Experts and representatives held in-depth discussions on theoretical study,

ESD Protection Design and Characteristic Analysis of Advanced Process Integrated Circuit

The electrostatic discharge(ESD)phenomenon is very common,in daily life,many places will appear ESD phenomenon.However,ESD is a potential hazard for integrated circuits.This paper analyzes the ESD protection design and characteristics of advanced process integrated circuits,and puts forward personal views combined with experience,hoping to bring help to the people who pay attention to the ESD protection of integrated circuits.

Protective Measures to Oil Depot Against Lightning Stroke and Electrostatic Spark

Introduction Lightning can cause great destruction. According to the record in the northern China, more than 150 lightning strokes occur on a power system annually. High voltage (millions of volts) and large current (hundreds of -kA) associated with lightning, will damage property and even kill people and livestocks. It will be very dangerous if a lightning stroke strikes oil depot of power plant or substation. In addition, the high voltage induced by the electrostatic charge generated due to oil flowing will probably cause damage unless the electrification has been limited and drained off.

High performance differential CMOS LNA design for low-IF GPS receiver

A 1.575 GHz CMOS （complementary metal-oxidesemiconductor transistor） low noise amplifier（LNA） suitable for a low intermediate frequency（IF） global positioning system（GPS） receiver is presented. Considering parasitic effects resulting from bond pad and input electrostatic discharge （ESD） protection diodes, the optimization of the input matching and noise performance is analyzed, and a narrowband inductor model is applied to the circuit design and optimization. Based on the Volterra series, the nonlinearity of the LNA is analyzed and an equation describing input-referred third-order intercept points （IIP3） which indicate the nonlinearity effects is derived; accordingly, the trade-off between the power consumption and linearity is made. The LNA is designed and simulated with TSMC （Taiwan Semiconductor Manufacturing Company） 0. 18 μm radio frequency （RF）technology. Simulation results show that the LNA has a noise figure of only 1.1 dB, - 8. 3 dBm IIP3 with 3 mA current consumption from a 1.8 V voltage supply, and the input impedances match well.

Low-leakage diode-triggered silicon controlled rectifier for electrostatic discharge protection in 0.18-μm CMOS process

A diode-triggered silicon controlled rectifier (DTSCR) is being developed as an electrostatic discharge (ESD) pro- tection device for low voltage applications. However, DTSCR leaks high current during normal operation due to the Darlington effect of the triggering-assist diode string. In this study, two types of diode string triggered SCRs are designed for low leakage consideration; the modified diode string and composite polysilicon diode string triggered SCRs (MDTSCR & PDTSCR). Com- pared with the conventional DTSCR (CDTSCR), the MDTSCR has a much lower substrate leakage current with a relatively large silicon cost, and the PDTSCR has a much lower substrate leakage current with similar area and shows good leakage performance at a high temperature. Other DTSCR ESD properties are also investigated, especially regarding their layout, triggering voltage and failure current.

ESD-Induced Noise to Low Noise Amplifier Circuits in BiCMOS

Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures （NFs） of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier （LNA） circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.