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Computer Network Control System in Automatic Automobile Detection
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作者 高岩 窦丽华 +1 位作者 高琪 周宁 《Journal of Beijing Institute of Technology》 EI CAS 2001年第4期406-411,共6页
An automobile test controlling and managing system with computer network is introduced. The architecture of the local network, hardware structure, software structure, design of the test process, and error tolerating r... An automobile test controlling and managing system with computer network is introduced. The architecture of the local network, hardware structure, software structure, design of the test process, and error tolerating redundant design in work position substituting are presented. At last, the pivotal questions solved are discussed. With an advanced structure, this system is multi functional and flexible. Furthermore, advanced computer technology is adopted to improve its technical degree. 展开更多
关键词 computer control system local network automobile test error tolerance
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Accuracy Analysis and Design of A3 Parallel Spindle Head 被引量:8
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作者 NI Yanbing ZHANG Biao +1 位作者 SUN Yupeng ZHANG Yuan 《Chinese Journal of Mechanical Engineering》 SCIE EI CAS CSCD 2016年第2期239-249,共11页
As functional components of machine tools, parallel mechanisms are widely used in high efficiency machining of aviation components, and accuracy is one of the critical technical indexes. Lots of researchers have focus... As functional components of machine tools, parallel mechanisms are widely used in high efficiency machining of aviation components, and accuracy is one of the critical technical indexes. Lots of researchers have focused on the accuracy problem of parallel mechanisms, but in terms of controlling the errors and improving the accuracy in the stage of design and manufacturing, further efforts are required. Aiming at the accuracy design of a 3-DOF parallel spindle head(A3 head), its error model, sensitivity analysis and tolerance allocation are investigated. Based on the inverse kinematic analysis, the error model of A3 head is established by using the first-order perturbation theory and vector chain method. According to the mapping property of motion and constraint Jacobian matrix, the compensatable and uncompensatable error sources which affect the accuracy in the end-effector are separated. Furthermore, sensitivity analysis is performed on the uncompensatable error sources. The sensitivity probabilistic model is established and the global sensitivity index is proposed to analyze the influence of the uncompensatable error sources on the accuracy in the end-effector of the mechanism. The results show that orientation error sources have bigger effect on the accuracy in the end-effector. Based upon the sensitivity analysis results, the tolerance design is converted into the issue of nonlinearly constrained optimization with the manufacturing cost minimum being the optimization objective. By utilizing the genetic algorithm, the allocation of the tolerances on each component is finally determined. According to the tolerance allocation results, the tolerance ranges of ten kinds of geometric error sources are obtained. These research achievements can provide fundamental guidelines for component manufacturing and assembly of this kind of parallel mechanisms. 展开更多
关键词 A3 head error model sensitivity analysis tolerance allocation
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LayCO:Achieving Least Lossy Accuracy for Most EfficientRRAM-Based Deep Neural Network Accelerator via Layer-Centric Co-Optimization
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作者 赵少锋 王芳 +2 位作者 刘博 冯丹 刘洋 《Journal of Computer Science & Technology》 SCIE EI CSCD 2023年第2期328-347,共20页
Resistive random access memory(RRAM)enables the functionality of operating massively parallel dot products and accumulations.RRAM-based accelerator is such an effective approach to bridging the gap between Internet of... Resistive random access memory(RRAM)enables the functionality of operating massively parallel dot products and accumulations.RRAM-based accelerator is such an effective approach to bridging the gap between Internet of Things devices’constrained resources and deep neural networks’tremendous cost.Due to the huge overhead of Analog to Digital(A/D)and digital accumulations,analog RRAM buffer is introduced to extend the processing in analog and in approximation.Although analog RRAM buffer offers potential solutions to A/D conversion issues,the energy consumption is still challenging in resource-constrained environments,especially with enormous intermediate data volume.Besides,critical concerns over endurance must also be resolved before the RRAM buffer could be frequently used in reality for DNN inference tasks.Then we propose LayCO,a layer-centric co-optimizing scheme to address the energy and endurance concerns altogether while strictly providing an inference accuracy guarantee.LayCO relies on two key ideas:1)co-optimizing with reduced supply voltage and reduced bit-width of accelerator architectures to increase the DNN’s error tolerance and achieve the accelerator’s energy efficiency,and 2)efficiently mapping and swapping individual DNN data to a corresponding RRAM partition in a way that meets the endurance requirements.The evaluation with representative DNN models demonstrates that LayCO outperforms the baseline RRAM buffer based accelerator by 27x improvement in energy efficiency(over TIMELY-like configuration),308x in lifetime prolongation and 6x in area reduction(over RAQ)while maintaining the DNN accuracy loss less than 1%. 展开更多
关键词 deep learning ACCELERATOR resistive random access memory(RRAM) energy efficiency error tolerance
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