Design Method of Anti-Total Ionizing Dose Effect Hardening for Buck-Boost Converter

Buck-Boost converter in the total dose radiation environment will mainly bring the output voltage drift, linear adjustment rate and load adjustment rate decline and other effects, so that the output stability performance of the circuit deteriorates. Aiming at the problems of high cost,large layout area and poor universality caused by the traditional total ionizing dose effect hardening method based on process and layout, this paper proposes a total ionizing dose effect hardening design method with parallel monitoring and hardening, which can achieve total ionizing dose effect hardening at the circuit level without process. The anti-total dose capability of Buck-Boost converter is improved. The circuit design and physical implementation of the proposed method are verified based on 0.18 μm bipolar complementary metal-oxide-semiconductor(CMOS) double-diffused metal-oxide-semiconductor(DMOS)(BCD) process. The results show that the system gain decrease rate can be compensated from 19.2% to 6.2%, and the output voltage shift rate can be improved from 2.00% to 0.15% at a dose of 200×10^(3) rad(Si). Moreover, the load adjustment rate and linear adjustment rate are reduced. They are respectively decreased to 0.191 %/A and 0.093 %/V. This provides a new idea for the design of total ionizing dose effect hardening at circuit and system level.

Design of a fast-transient and high-stabilized GPS low dropout regulator

A high stabilized low dropout(LDO) voltage regulator fabricated for GPS radio frequency(RF) chip in SMIC 0.18μm CMOS technology is presented.The LDO mainly consists of bandgap reference,error amplifier,resistive feedback network and AC current path.A fast current path is added to improve the performance of LDO's transient response.Equivalent series resistance(ESR)compensation and internal Miller compensation are used to constitute the frequency compensation.The measurement results of the transient response of the output voltage show that it can recover within 2μs with less than 120 mV ripple when the load current is changed from 0 to 100 mA.The total quiescent current of LDO and bandgap reference(without load) is 260 μA.

A 1.8V LDO voltage regulator with foldback current limit and thermal protection

This paper introduces the design of a l.8 V low dropout voltage regulator （LDO） and a foldback current limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in a 0.18 μm CMOS technology. The measured result reveals that the LDO s power supply rejection （PSR） is about -58dB and -54dB at 20Hz and 1kHz respectively,the response time is 4μs and the quiescent currentis 20μA. The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a maximum load current of 240 mA.

Low-power variable frequency PFC converters

Based on the SinoMOS 1 μm 40 V CMOS process, a novel power factor corrention （PFC） converter with a low-power variable frequency function is presented. The circuit introduces a multi-vector error amplifier and a programmable oscillator to achieve frequency modulation, which provides a rapid dynamic response and precise output voltage clamping with low power in the entire load. According to the external load variation, the system can modulate the circuit operating frequency linearly, thereby ensuring that the PFC converter can work in frequency conversionmode. Measured results show that the normal operating frequency of the PFC converter is 5-6 kHz, the start-up current is 36 μA, the stable operating current is only 2.43 mA, the efficiency is 97.3%, the power factor （PF） is 0.988, THD is 3.8%, the load adjust rate is 3%, and the linear adjust rate is less than 1%. Both theoretical and practical results reveal that the power consumption of the whole supply system is reduced efficiently, especially when the load varies. The active die area of the PFC converter chip is 1.61 ×1.52 mm^2.