在现有全加器研究基础上,提出一种高性能全加器改进电路(improved full adder circuit,IFAC),通过改进全加器电路结构,优化电路元件工作数量,旨在提升加法器逻辑功能与运行状态。采用Candence软件搭载130 nm芯片锻造工艺,引入欧拉路径...在现有全加器研究基础上,提出一种高性能全加器改进电路(improved full adder circuit,IFAC),通过改进全加器电路结构,优化电路元件工作数量,旨在提升加法器逻辑功能与运行状态。采用Candence软件搭载130 nm芯片锻造工艺,引入欧拉路径快速判寻法设计其电路版图,验证版图规则的合理性,并利用版图验证工具Dracula对电路进行仿真测试,结果表明本文所设计的全加器较常规全加器在处理复杂网络精确度、传输延迟时间、低功耗稳定运行及芯片面积方面有所提升。展开更多
The embedding technique based on an operator appeared in [Liu, Y. P., Scientia Sinica, Special Issue on Math,1 (1979),191-201 (in Chinese)] for determining the maximum non-orientable genus of a graph is developed to o...The embedding technique based on an operator appeared in [Liu, Y. P., Scientia Sinica, Special Issue on Math,1 (1979),191-201 (in Chinese)] for determining the maximum non-orientable genus of a graph is developed to obtain the general theorem which presents a necessary and sufficient condition for a graph to be embeddable into either the orientable or the non-orientable surface of genus k. Furthermore,the greatest lower bound of the lengths of genus ranges of the class of nonplanar graphs which are up-embeddable is also obtained.展开更多
文摘在现有全加器研究基础上,提出一种高性能全加器改进电路(improved full adder circuit,IFAC),通过改进全加器电路结构,优化电路元件工作数量,旨在提升加法器逻辑功能与运行状态。采用Candence软件搭载130 nm芯片锻造工艺,引入欧拉路径快速判寻法设计其电路版图,验证版图规则的合理性,并利用版图验证工具Dracula对电路进行仿真测试,结果表明本文所设计的全加器较常规全加器在处理复杂网络精确度、传输延迟时间、低功耗稳定运行及芯片面积方面有所提升。
文摘The embedding technique based on an operator appeared in [Liu, Y. P., Scientia Sinica, Special Issue on Math,1 (1979),191-201 (in Chinese)] for determining the maximum non-orientable genus of a graph is developed to obtain the general theorem which presents a necessary and sufficient condition for a graph to be embeddable into either the orientable or the non-orientable surface of genus k. Furthermore,the greatest lower bound of the lengths of genus ranges of the class of nonplanar graphs which are up-embeddable is also obtained.