MOS bulk transistor is reaching its limits： sub-threshold slope （SS）, drain induced barrier lowering （DIBL）, threshold voltage （VT） and VDD scaling slowing down, more power dissipation, less speed gain, less ac...MOS bulk transistor is reaching its limits： sub-threshold slope （SS）, drain induced barrier lowering （DIBL）, threshold voltage （VT） and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide （BOx）. Called ultra thin body and buried oxide （UTBB） transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator （VCO） based on a ring oscillator （RO） designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about -94 dBc/Hz@l MHz.展开更多
In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have bee...In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have been investigated by 3D TCAD simulations.The critical charges and SEU threshold linear energy transfer(LET) value of the two SRAM cells are consistent due to similar gate capacitance.The low electrical field and the high recombination rate account for the non-sensitivity to SEU in heavily doped drain region.Compared with FDSOI SRAM,SOI FinFET SRAM cell exhibits lower SEU sensitivity at the center of the gate.The smaller sensitive area in SOI FinFET SRAM cell may result in a smaller SEU saturation cross section than that of SOI FinFET SRAM.展开更多
A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by...A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.展开更多
TiN gate thin-film fully-depleted SOI CMOS devices are fabricated and discussed.Key process technologies are demonstrated.Compared with the dual polysilicon gate devices,the channel doping concentration of nMOS and pM...TiN gate thin-film fully-depleted SOI CMOS devices are fabricated and discussed.Key process technologies are demonstrated.Compared with the dual polysilicon gate devices,the channel doping concentration of nMOS and pMOS can be reduced without changing threshold voltage (V T),which enhances the mobility.Symmetrical V T is achieved by nearly the same V T implant dose because of the near mid-gap workfunction of TiN gate.The SCE effect is improved when the thin-film thickness is reduced.展开更多
m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the ...m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade.The saturation current of 1.2μm nMOSFETs is increased by 32% with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%.The per-stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.展开更多
文摘MOS bulk transistor is reaching its limits： sub-threshold slope （SS）, drain induced barrier lowering （DIBL）, threshold voltage （VT） and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide （BOx）. Called ultra thin body and buried oxide （UTBB） transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator （VCO） based on a ring oscillator （RO） designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about -94 dBc/Hz@l MHz.
基金supported by the National Natural Science Foundation of China (Grant No. 11175138)the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20100201110018)the Key Program of the National Natural Science Foundation of China (Grant No. 11235008)
文摘In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have been investigated by 3D TCAD simulations.The critical charges and SEU threshold linear energy transfer(LET) value of the two SRAM cells are consistent due to similar gate capacitance.The low electrical field and the high recombination rate account for the non-sensitivity to SEU in heavily doped drain region.Compared with FDSOI SRAM,SOI FinFET SRAM cell exhibits lower SEU sensitivity at the center of the gate.The smaller sensitive area in SOI FinFET SRAM cell may result in a smaller SEU saturation cross section than that of SOI FinFET SRAM.
文摘A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.
文摘TiN gate thin-film fully-depleted SOI CMOS devices are fabricated and discussed.Key process technologies are demonstrated.Compared with the dual polysilicon gate devices,the channel doping concentration of nMOS and pMOS can be reduced without changing threshold voltage (V T),which enhances the mobility.Symmetrical V T is achieved by nearly the same V T implant dose because of the near mid-gap workfunction of TiN gate.The SCE effect is improved when the thin-film thickness is reduced.
文摘m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade.The saturation current of 1.2μm nMOSFETs is increased by 32% with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%.The per-stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.
