FPGA Implementation of Extended Kalman Filter for Parameters Estimation of Railway Wheelset

It is necessary to know the status of adhesion conditions between wheel and rail for efficient accelerating and decelerating of railroad vehicle.The proper estimation of adhesion conditions and their real-time implementation is considered a challenge for scholars.In this paper,the development of simulation model of extended Kalman filter(EKF)in MATLAB/Simulink is presented to estimate various railway wheelset parameters in different contact conditions of track.Due to concurrent in nature,the Xilinx®System-on-Chip Zynq Field Programmable Gate Array(FPGA)device is chosen to check the onboard estimation ofwheel-rail interaction parameters by using the National Instruments(NI)myRIO®development board.The NImyRIO®development board is flexible to deal with nonlinearities,uncertain changes,and fastchanging dynamics in real-time occurring in wheel-rail contact conditions during vehicle operation.The simulated dataset of the railway nonlinear wheelsetmodel is tested on FPGA-based EKF with different track conditions and with accelerating and decelerating operations of the vehicle.The proposed model-based estimation of railway wheelset parameters is synthesized on FPGA and its simulation is carried out for functional verification on FPGA.The obtained simulation results are aligned with the simulation results obtained through MATLAB.To the best of our knowledge,this is the first time study that presents the implementation of a model-based estimation of railway wheelset parameters on FPGA and its functional verification.The functional behavior of the FPGA-based estimator shows that these results are the addition of current knowledge in the field of the railway.

Design and FPGA Implementation of a new hyperchaotic system

In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array （FPGA） technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup.

Study on a new chaotic bitwise dynamical system and its FPGA implementation

In this paper, the structure of a new chaotic bitwise dynamical system （CBDS） is described. Compared to our previous research work, it uses various random bitwise operations instead of only one. The chaotic behavior of CBDS is mathemat- ically proven according to the Devaney＇s definition, and its statistical properties are verified both for uniformity and by a comprehensive, reputed and stringent battery of tests called TestU01. Furthermore, a systematic methodology developing the parallel computations is proposed for FPGA platform-based realization of this CBDS. Experiments finally validate the proposed systematic methodology.

Heterogeneous dual memristive circuit:Multistability,symmetry,and FPGA implementation

An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the engineering applications,the 3 rd-order model(3 OM)in flux-charge domain is derived from the 5 th-order model(5 OM)in volt-ampere domain by using the flux-charge analysis method(FCAM).The consistence of symmetry and multistability before and after dimensionality decreasing is meticulously investigated via bifurcation diagram,Lyapunov exponents,and especially attraction basins.The comparative analysis validates the effectiveness of reduction model and improves the controllability of the circuit.To avoid the noise in the analog circuit,a field-programmable gate array(FPGA)is utilized to realize the reduction model,which is rarely reported and valuable for relevant research and application.

Efficient FPGA implementation of AES 128 bit for IEEE 802.16e mobile WiMax standards

In an advancement of communication field, wireless technology plays a predominant role in data transmission. In the timeline of wireless domain, Wi-Fi, Bluetooth, zigbee etc are some of the standards, which are being used in today’s wireless medium. In addition, the WiMax is introduced by IEEE in IEEE 802.16 for long distance communication, specifically 802.16e standard for mobile WiMax. It is an acronym of Worldwide Interoperability for Microwave Access. It is to be deliver wireless transmission with high quality of service in a secured environment. Since, security becomes dominant design aspect of every communication, a new technique has been proposed in wireless environment. Privacy across the network and access control management is the goal in the predominant aspects in the WiMax protocol. Especially, MAC sub layer should be evaluated in the security architecture. It has been proposed on cryptography algorithm AES that require high cost. Under this scenario, we present the optimized AES 128 bit counter mode security algorithm for MAC layer of 802.16e standards. To design a efficient MAC layer, we adopt the modification of security layers data handling process. As per the efficient design strategy, the power and speed are the dominant factors in mobile device. Since we concentrate mobile WiMax, efficient design is needed for MAC Security layer. Our proposed model incorporates the modification of AES algorithm. The design has been implemented in Xilinx virtex5 device and power has been analyzed using XPower analyzer. This proposed system consumes 41% less power compare to existing system.

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.

Dynamic analysis,FPGA implementation,and cryptographic application of an autonomous 5D chaotic system with offset boosting

An autonomous five-dimensional(5D)system with offset boosting is constructed by modifying the well-known three-dimensional autonomous Liu and Chen system.Equilibrium points of the proposed autonomous 5D system are found and its stability is analyzed.The proposed system includes Hopf bifurcation,periodic attractors,quasi-periodic attractors,a one-scroll chaotic attractor,a double-scroll chaotic attractor,coexisting attractors,the bistability phenomenon,offset boosting with partial amplitude control,reverse period-doubling,and an intermittency route to chaos.Using a field programmable gate array(FPGA),the proposed autonomous 5D system is implemented and the phase portraits are presented to check the numerical simulation results.The chaotic attractors and coexistence of the attractors generated by the FPGA implementation of the proposed system have good qualitative agreement with those found during the numerical simulation.Finally,a sound data encryption and communication system based on the proposed autonomous 5D chaotic system is designed and illustrated through a numerical example.

A SWITCHED HYPERCHAOTIC SYSTEM AND ITS FPGA CIRCUITRY IMPLEMENTATION

This paper introduces a switched hyperchaotic system that changes its behavior randomly from one subsystem to another via two switch functions, and its characteristics of symmetry, dissipation, equilibrium, bifurcation diagram, basic dynamics have been analyzed. The hardware implementation of the system is based on Field Programmable Gate Array (FPGA). It is shown that the experimental results are identical with numerical simulations, and the chaotic trajectories are much more complex.

Memristor hyperchaos in a generalized Kolmogorov-type system with extreme multistability

Memristor chaotic systems have aroused great attention in recent years with their potentials expected in engineering applications.In this paper,a five-dimension(5D)double-memristor hyperchaotic system(DMHS)is modeled by introducing two active magnetron memristor models into the Kolmogorov-type formula.The boundness condition of the proposed hyperchaotic system is proved.Coexisting bifurcation diagram and numerical verification explain the bistability.The rich dynamics of the system are demonstrated by the dynamic evolution map and the basin.The simulation results reveal the existence of transient hyperchaos and hidden extreme multistability in the presented DMHS.The NIST tests show that the generated signal sequence is highly random,which is feasible for encryption purposes.Furthermore,the system is implemented based on a FPGA experimental platform,which benefits the further applications of the proposed hyperchaos.

Secure and efficient implementation of facial emotion detection for smart patient monitoring system

Background:Machine learning has enabled the automatic detection of facial expressions,which is particularly beneficial in smart monitoring and understanding the mental state of medical and psychological patients.Most algorithms that attain high emotion classification accuracy require extensive computational resources,which either require bulky and inefficient devices or require the sensor data to be processed on cloud servers.However,there is always the risk of privacy invasion,data misuse,and data manipulation when the raw images are transferred to cloud servers for processing facical emotion recognition(FER)data.One possible solution to this problem is to minimize the movement of such privatedata.Methods:In this research,we propose an efficient implementation of a convolutional neural network(CNN)based algorithm for on-device FER on a low-power field programmable gate array(FPGA)platform.This is done by encoding the CNN weights to approximated signed digits,which reduces the number of partial sums to be computed for multiply-accumulate(MAC)operations.This is advantageous for portable devices that lack full-fledged resourceintensivemultipliers.Results:We applied our approximation method on MobileNet-v2 and ResNet18 models,which were pretrained with the FER2013 dataset.Our implementations and simulations reduce the FPGA resource requirement by at least 22%compared to models with integer weight,with negligible loss in classification accuracy.Conclusions:The outcome of this research will help in the development of secure and low-power systems for FER and other biomedical applications.The approximation methods used in this research can also be extended to other imagebasedbiomedicalresearchfields.

Development of a Multi-DOF Robotic Controller for Academic Purposes

This article presents the development of a robotic controller for technical training, academic teaching, and research. The controller was designed to interact from 1 to 6 DOF （degrees of freedom） serial robotic arms, actuated by brushed DC （direct current） servomotors equipped with incremental encoders. Controller architecture is based on four components： a processor, a reconfigurable FPGA （field-programmable gate array）, measurement I/O hardware and software. Functionality of the robotic controller has been proved by means of the interaction with an SCARA （selective compliance assembly robot arm）. The proposed controller presents the potential to teach technical courses （like robotics, control, electronics and programming） and to implement and validate advanced control algorithms.