Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.

GJB 5000B在FPGA工程中的应用分析

为引入软件工程化管理办法对设计开发实践实施管理,结合GJB 5000B体系要求,对现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的设计开发流程和GJB 5000B的工程实践要求进行梳理、比对和分析,并提出一套FPGA开发管理在GJB 5000B推进实践中的实施办法。研究成果可为GJB 5000B在FPGA工程中的应用提供一定参考。

A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA)

In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.

FPGA-based acceleration for binary neural networks in edge computing

As a core component in intelligent edge computing,deep neural networks(DNNs)will increasingly play a critically important role in addressing the intelligence-related issues in the industry domain,like smart factories and autonomous driving.Due to the requirement for a large amount of storage space and computing resources,DNNs are unfavorable for resource-constrained edge computing devices,especially for mobile terminals with scarce energy supply.Binarization of DNN has become a promising technology to achieve a high performance with low resource consumption in edge computing.Field-programmable gate array(FPGA)-based acceleration can further improve the computation efficiency to several times higher compared with the central processing unit(CPU)and graphics processing unit(GPU).This paper gives a brief overview of binary neural networks(BNNs)and the corresponding hardware accelerator designs on edge computing environments,and analyzes some significant studies in detail.The performances of some methods are evaluated through the experiment results,and the latest binarization technologies and hardware acceleration methods are tracked.We first give the background of designing BNNs and present the typical types of BNNs.The FPGA implementation technologies of BNNs are then reviewed.Detailed comparison with experimental evaluation on typical BNNs and their FPGA implementation is further conducted.Finally,certain interesting directions are also illustrated as future work.

SRAM型FPGA单粒子辐照试验系统技术研究

单粒子辐射效应严重制约FPGA的空间应用,为提高FPGA在辐射环境中的可靠性,深入研究抗辐射加固FPGA单粒子效应评估方法,设计优化单粒子效应评估方案,开发相应的评估系统,提出基于SRAM时序修正的码流存储比较技术和基于SelectMAP端口配置回读技术。借助国内高能量大注量率的辐照试验环境,完成FPGA单粒子翻转(SEU)、单粒子闩锁(SEL)和单粒子功能中断(SEFI)等单粒子效应的检测,试验结果表明,该方法可以科学有效地对SRAM型FPGA抗单粒子辐射性能进行评估。

阻塞斩波三相交交变频电源的FPGA控制实现

变频技术是重要的节能技术,所以针对低频或转速不恒定的节能设备,提出了基于FPGA数字控制的三相交交直接变频电源技术。用VHDL语言对主控芯片FPGA编写程序,其输出的高频SPWM信号经驱动电路后作为电源和负载间开关MOSFET的控制信号。MOSFET周期性地部分阻塞电源不能达到负载来改变输出电压的频率,同时在放行的时区斩波来改变输出电压的幅值。基于Matlab仿真平台,对系统进行了建模和仿真,仿真结果验证了该技术的正确性。最后给出了频率为7.14 Hz和2.63 Hz的实验波形,实验结果证明了该技术的可行性。

Design of IP core for IIC bus controller based on FPGA

The intellectual property （IP） core for inter-integrated circuit （IIC） bus controller is designed using finite state machine （FSM） based on field programmable gate array （FPGA）. Not only the data from AT 24C02C can be read automatically after power on, but also the data from upper computer can be written into AT24C02C immediately under the control of the IIC bus controller. When it is applied to blast wave overpressure test system, the IIC bus controller can read and store working parameters automatically. In a laboratory environment, the IP core simulation is carried out and the result is accurate. In the explosion field test, by analyzing the obtained valid data, it can be concluded that the designed IP core has good reliability.

10 Gbit/s PRBS tester implemented in FPGA

The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.

FPGA implementation of bit-stream neuron and perceptron based on sigma delta modulation

To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.

大尺寸机载显示模块动态背光控制系统设计

机载大尺寸液晶显示器(liquid crystal display,LCD)显示模块具有亮度高和功耗大的特点。为了降低其动态功耗,介绍了一种用于大尺寸机载显示模块的动态背光控制系统。该系统采用发光二极管(light emitting diode,LED)动态背光控制技术,通过对背光的动态调节,提高动态显示效果和达到节能的目的。对系统的硬件电路和软件设计算法进行了详细的介绍,并进行实验验证。结果表明,该系统能够有效地提高机载显示模块的动态显示效果,并显著降低了动态功耗。

GPS P码接收机本地信号发生器的FPGA实现

P码作为GPS军用伪码,具有结构复杂、周期长且码速率快的特点,这使得使用P码的软件接收机不仅定位精度高,且具有很强的抗干扰和反欺骗能力。能够实现任意卫星的任意时刻P码的产生,对于实现P码直接捕获和跟踪有很重要的意义。对于P码的产生原理和结构进行了分析,基于MATLAB设计了相应的P码发生算法并进行简单的算法仿真。之后针对FPGA硬件平台对P码发生器进行了相应的模块设计,包含寄存器模块、延时模块、周期控制模块和寄存器相位模块等。测试实验结果表明P码发生器可以基本无延迟地生成任意卫星、任意时刻的P码。

Mosaic line-scan camera based on FPGA

Because single line-scan camera loses light in the edge of the sensor when the field of view is large, a mosaic cam- era based on field programmable gate array （FPGA） is presented by putting multiple cameras arranged in a straight line to share the field of view and reduce the view angle of every camera. For detecting doping micro particles with the designed mosaic line-scan camera, a detection algorithm of the target＇s location in FPGA is proposed. Finally, the practicability and stability of the system were validated experimentally. The results of the experiment show that the camera can get images clearly with less light loss and can accurately distinguish the target and the background.

Design of IRIG-B(AC) encoder based on FPGA

InterRange Instrumentation Group（IRIG-B（AC））code is usually used in the shooting range test for time information transmission and systems time synchronization.According to IRIG-B（AC）code format and modulation principle,this paper presents IRIG-B（AC）coding circuit design scheme based on field programmable gate array（FPGA）.The B（AC）code signal is generated by AD7245,a digital-to-analog（D/A）converter.After amplified,the signal can be used directly for system time synchronization,and the amplitude of the signal can be adjusted according to different requirements.The IRIG-B（AC）encoder designed has been verified by test.The test results show that it can output accurate time information and has higher practicality.

双磁控忆阻器动力学模型及FPGA硬件电路实现

基于经典Chua混沌电路设计了一个五维双磁控忆阻器混沌电路。对电路非线性特性进行数值分析,表明其具有丰富的混沌动力学行为。采用一阶离散处理对电路进行数字化转换,基于DSP Builder和FPGA(Field Programmable Gate Array)技术,通过CycloneⅣE系列EP4CE10F17C8N芯片搭建的硬件平台,真实实现了该模型数字化系统。设计结果表明,数字化忆阻器系统避免了模拟信号元器件的漂移和不稳定性,硬件波形显示性能稳定可靠,且与计算机仿真结果具有相当一致性的吻合。

基于FPGA的控制算法定点化设计

运动控制算法在现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)上实现过程中,当数据类型由浮点转定点时,存在无法保证高精度的问题。为此使用simulink中的定点工具(Fixed-Point Tool)对算法内部各信号数据的范围进行分析,然后人为地对Fixed-Point Tool给出的建议位宽进行修正,从而使算法在保证较高精度的同时,也解决了采用统一较长位宽在FPGA上实现时造成的资源浪费问题。与传统的人为定义数据位宽相比,使用Fixed-Point Tool设置数据位宽,在输入数据范围发生变化时,能够更加灵活、动态地调整算法内部数据位宽。

Implementation of encoder and decoder for LDPC codes based on FPGA

This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.

基于Xilinx型FPGA系统单粒子效应评估方法研究

Virtex-5系列芯片没有官方提供的专用软错误缓解(Soft Error Mitigation,SEM)IP核,需自行设计故障注入系统.本文选用XC5VFX130T型现场可编程门阵列(Field Programmable Gate Array,FPGA)芯片利用单帧部分重构功能达到等同于SEM IP故障注入效果,实现对FPGA电路系统的抗单粒子翻转能力评估测试.利用逐位注入故障模式对XC5VFX130T型FPGA的配置位逐个注入故障,获得待评估电路的敏感配置位信息;对待测电路进行三模冗余防护加固,利用累积故障注入模式连续随机注入模拟单粒子辐照试验环境,得到待评估电路的功能中断截面,进而实现对基于XC5VFX130T型FPGA系统的抗单粒子翻转加固效果的评估.研究表明,基准电路(移位寄存器链等)评估得到的功能中断截面与实际辐照试验中的功能中断截面曲线变化一致,为机载电子的单粒子效应适航评估提供了支持.

REVIEW OF ADVANCED FPGA ARCHITECTURES AND TECHNOLOGIES

Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.

Searching for complete set of free resource rectangles on FPGA area based on CPTR

As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.

FPGA-Based Efficient Programmable Polyphase FIR Filter

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)