The globalization of hardware designs and supply chains,as well as the integration of third-party intellectual property(IP)cores,has led to an increased focus from malicious attackers on computing hardware.However,exi...The globalization of hardware designs and supply chains,as well as the integration of third-party intellectual property(IP)cores,has led to an increased focus from malicious attackers on computing hardware.However,existing defense or detection approaches often require additional circuitry to perform security verification,and are thus constrained by time and resource limitations.Considering the scale of actual engineering tasks and tight project schedules,it is usually difficult to implement designs for all modules in field programmable gate array(FPGA)circuits.Some studies have pointed out that the failure of key modules tends to cause greater damage to the network.Therefore,under limited conditions,priority protection designs need to be made on key modules to improve protection efficiency.We have conducted research on FPGA designs including single FPGA systems and multi-FPGA systems,to identify key modules in FPGA systems.For the single FPGA designs,considering the topological structure,network characteristics,and directionality of FPGA designs,we propose a node importance evaluationmethod based on the technique for order preference by similarity to an ideal solution(TOPSIS)method.Then,for the multi-FPGA designs,considering the influence of nodes in intra-layer and inter-layers,they are constructed into the interdependent network,and we propose a method based on connection strength to identify the important modules.Finally,we conduct empirical research using actual FPGA designs as examples.The results indicate that compared to other traditional indexes,node importance indexes proposed for different designs can better characterize the importance of nodes.展开更多
为提高电信网设备应对异常信令访问的检测能力,需对64K信令进行分析并处理。为了提高解析效率并满足近年来相关产品对自主可控越来越高的要求,设计了一种基于国产现场可编程门阵列(Field Programmable Gate Array, FPGA)的信令解析方案...为提高电信网设备应对异常信令访问的检测能力,需对64K信令进行分析并处理。为了提高解析效率并满足近年来相关产品对自主可控越来越高的要求,设计了一种基于国产现场可编程门阵列(Field Programmable Gate Array, FPGA)的信令解析方案,给出了方案的总体设计思路,并对FPGA实现的功能模块进行详细说明。对系统进行设计时,采用模块化参数化方法以及在关键环节添加状态参数,提高了可扩展性并可以对模块内部运行状态进行监控,最终实现了对信令高效且灵活的解析,主要器件等均为国产。经过测试,可以实现STM-1(STM-Synchronous Transfer Module-1)数据的接入、串并转换、HDLC(High-level Data Link Control)解帧等功能,完成32路64K信令的并发处理,模块运行状态可查可看,达到了预期的效果。以STM-1为例,基于现有功能的模块化设计,可以平滑地扩展到STM-4、STM-16的应用。展开更多
基金supported by the Natural Science Foundation of China under Grant Nos.62362008,61973163,61972345,U1911401.
文摘The globalization of hardware designs and supply chains,as well as the integration of third-party intellectual property(IP)cores,has led to an increased focus from malicious attackers on computing hardware.However,existing defense or detection approaches often require additional circuitry to perform security verification,and are thus constrained by time and resource limitations.Considering the scale of actual engineering tasks and tight project schedules,it is usually difficult to implement designs for all modules in field programmable gate array(FPGA)circuits.Some studies have pointed out that the failure of key modules tends to cause greater damage to the network.Therefore,under limited conditions,priority protection designs need to be made on key modules to improve protection efficiency.We have conducted research on FPGA designs including single FPGA systems and multi-FPGA systems,to identify key modules in FPGA systems.For the single FPGA designs,considering the topological structure,network characteristics,and directionality of FPGA designs,we propose a node importance evaluationmethod based on the technique for order preference by similarity to an ideal solution(TOPSIS)method.Then,for the multi-FPGA designs,considering the influence of nodes in intra-layer and inter-layers,they are constructed into the interdependent network,and we propose a method based on connection strength to identify the important modules.Finally,we conduct empirical research using actual FPGA designs as examples.The results indicate that compared to other traditional indexes,node importance indexes proposed for different designs can better characterize the importance of nodes.
文摘为提高电信网设备应对异常信令访问的检测能力,需对64K信令进行分析并处理。为了提高解析效率并满足近年来相关产品对自主可控越来越高的要求,设计了一种基于国产现场可编程门阵列(Field Programmable Gate Array, FPGA)的信令解析方案,给出了方案的总体设计思路,并对FPGA实现的功能模块进行详细说明。对系统进行设计时,采用模块化参数化方法以及在关键环节添加状态参数,提高了可扩展性并可以对模块内部运行状态进行监控,最终实现了对信令高效且灵活的解析,主要器件等均为国产。经过测试,可以实现STM-1(STM-Synchronous Transfer Module-1)数据的接入、串并转换、HDLC(High-level Data Link Control)解帧等功能,完成32路64K信令的并发处理,模块运行状态可查可看,达到了预期的效果。以STM-1为例,基于现有功能的模块化设计,可以平滑地扩展到STM-4、STM-16的应用。
