A Universal BIST Approach for Virtex-Ultrascale Architecture

Interconnected cells,Configurable Logic Blocks(CLBs),and input/output(I/O)pads are all present in every Field Programmable Gate Array(FPGA)structure.The interconnects are formed by the physical paths for connecting the blocks.The combinational and sequential circuits are used in the logic blocks to execute logical functions.The FPGA includes two different tests called interconnect testing and logical testing.Instead of using an additional circuitry,the Built-in-Self-Test(BIST)logic is coded into an FPGA,which is then reconfigured to perform its specific operation after the testing is completed.As a result,additional test circuits for the FPGA board are no longer required.The FPGA BIST has no area overhead or performance reduction issues like conventional BIST.A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation.In this work,the Configurable Logic Blocks(CLBs)of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture.To evaluate the CLBs’capabilities including distributed modes of operation of Random Access Memory(RAM),several types of configurations are created.These setups have the ability to identify 100%stuck-at failures in every CLB.This method is suitable for all phases of FPGA testing and has no overhead or performance cost.

A Test Approach for Look-Up Table Based FPGAs

This paper describes a test architecture for minimum number of test configurations in test of FPGA （Field Programmable Gate Array） LUTs （Look Up Tables）. The test architecture includes a TPG （Test Pattern Generator） that is tested while it is generating test data for LEs （Logic Elements） that form the CUT （Circuit Under Test）. This scheme eliminates the need for switching LEs between CUT, TPG and ORA （Output Response Analyzer） and having to perform many more reconfiguratioas of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, a scheme is presented for testing other parts of LEs. Compared with other methods, the presented scheme uses the least number of reconfigurations of an FPGA for its LUT testing.