An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the ...An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the engineering applications,the 3 rd-order model(3 OM)in flux-charge domain is derived from the 5 th-order model(5 OM)in volt-ampere domain by using the flux-charge analysis method(FCAM).The consistence of symmetry and multistability before and after dimensionality decreasing is meticulously investigated via bifurcation diagram,Lyapunov exponents,and especially attraction basins.The comparative analysis validates the effectiveness of reduction model and improves the controllability of the circuit.To avoid the noise in the analog circuit,a field-programmable gate array(FPGA)is utilized to realize the reduction model,which is rarely reported and valuable for relevant research and application.展开更多
A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree repres...A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.展开更多
With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledg...With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.展开更多
The globalization of hardware designs and supply chains,as well as the integration of third-party intellectual property(IP)cores,has led to an increased focus from malicious attackers on computing hardware.However,exi...The globalization of hardware designs and supply chains,as well as the integration of third-party intellectual property(IP)cores,has led to an increased focus from malicious attackers on computing hardware.However,existing defense or detection approaches often require additional circuitry to perform security verification,and are thus constrained by time and resource limitations.Considering the scale of actual engineering tasks and tight project schedules,it is usually difficult to implement designs for all modules in field programmable gate array(FPGA)circuits.Some studies have pointed out that the failure of key modules tends to cause greater damage to the network.Therefore,under limited conditions,priority protection designs need to be made on key modules to improve protection efficiency.We have conducted research on FPGA designs including single FPGA systems and multi-FPGA systems,to identify key modules in FPGA systems.For the single FPGA designs,considering the topological structure,network characteristics,and directionality of FPGA designs,we propose a node importance evaluationmethod based on the technique for order preference by similarity to an ideal solution(TOPSIS)method.Then,for the multi-FPGA designs,considering the influence of nodes in intra-layer and inter-layers,they are constructed into the interdependent network,and we propose a method based on connection strength to identify the important modules.Finally,we conduct empirical research using actual FPGA designs as examples.The results indicate that compared to other traditional indexes,node importance indexes proposed for different designs can better characterize the importance of nodes.展开更多
为提高电信网设备应对异常信令访问的检测能力,需对64K信令进行分析并处理。为了提高解析效率并满足近年来相关产品对自主可控越来越高的要求,设计了一种基于国产现场可编程门阵列(Field Programmable Gate Array, FPGA)的信令解析方案...为提高电信网设备应对异常信令访问的检测能力,需对64K信令进行分析并处理。为了提高解析效率并满足近年来相关产品对自主可控越来越高的要求,设计了一种基于国产现场可编程门阵列(Field Programmable Gate Array, FPGA)的信令解析方案,给出了方案的总体设计思路,并对FPGA实现的功能模块进行详细说明。对系统进行设计时,采用模块化参数化方法以及在关键环节添加状态参数,提高了可扩展性并可以对模块内部运行状态进行监控,最终实现了对信令高效且灵活的解析,主要器件等均为国产。经过测试,可以实现STM-1(STM-Synchronous Transfer Module-1)数据的接入、串并转换、HDLC(High-level Data Link Control)解帧等功能,完成32路64K信令的并发处理,模块运行状态可查可看,达到了预期的效果。以STM-1为例,基于现有功能的模块化设计,可以平滑地扩展到STM-4、STM-16的应用。展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61971228 and 61871230)the Natural Science Foundations of Jiangsu Higher Education Institutions,China(Grant No.19KJB520042)the Postgraduate Research&Practice Innovation Program of Jiangsu Province,China(Grant No.SJCX210564)。
文摘An improved heterogeneous dual memristive circuit(DMC)is proposed based on Chua's circuit,which shows good symmetry and multistablility.For the difficulty in controlling the initial conditions,which restricts the engineering applications,the 3 rd-order model(3 OM)in flux-charge domain is derived from the 5 th-order model(5 OM)in volt-ampere domain by using the flux-charge analysis method(FCAM).The consistence of symmetry and multistability before and after dimensionality decreasing is meticulously investigated via bifurcation diagram,Lyapunov exponents,and especially attraction basins.The comparative analysis validates the effectiveness of reduction model and improves the controllability of the circuit.To avoid the noise in the analog circuit,a field-programmable gate array(FPGA)is utilized to realize the reduction model,which is rarely reported and valuable for relevant research and application.
基金Supported by the National Natural Science Foundation of China(61271113)
文摘A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.
文摘With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.
基金supported by the Natural Science Foundation of China under Grant Nos.62362008,61973163,61972345,U1911401.
文摘The globalization of hardware designs and supply chains,as well as the integration of third-party intellectual property(IP)cores,has led to an increased focus from malicious attackers on computing hardware.However,existing defense or detection approaches often require additional circuitry to perform security verification,and are thus constrained by time and resource limitations.Considering the scale of actual engineering tasks and tight project schedules,it is usually difficult to implement designs for all modules in field programmable gate array(FPGA)circuits.Some studies have pointed out that the failure of key modules tends to cause greater damage to the network.Therefore,under limited conditions,priority protection designs need to be made on key modules to improve protection efficiency.We have conducted research on FPGA designs including single FPGA systems and multi-FPGA systems,to identify key modules in FPGA systems.For the single FPGA designs,considering the topological structure,network characteristics,and directionality of FPGA designs,we propose a node importance evaluationmethod based on the technique for order preference by similarity to an ideal solution(TOPSIS)method.Then,for the multi-FPGA designs,considering the influence of nodes in intra-layer and inter-layers,they are constructed into the interdependent network,and we propose a method based on connection strength to identify the important modules.Finally,we conduct empirical research using actual FPGA designs as examples.The results indicate that compared to other traditional indexes,node importance indexes proposed for different designs can better characterize the importance of nodes.
文摘为提高电信网设备应对异常信令访问的检测能力,需对64K信令进行分析并处理。为了提高解析效率并满足近年来相关产品对自主可控越来越高的要求,设计了一种基于国产现场可编程门阵列(Field Programmable Gate Array, FPGA)的信令解析方案,给出了方案的总体设计思路,并对FPGA实现的功能模块进行详细说明。对系统进行设计时,采用模块化参数化方法以及在关键环节添加状态参数,提高了可扩展性并可以对模块内部运行状态进行监控,最终实现了对信令高效且灵活的解析,主要器件等均为国产。经过测试,可以实现STM-1(STM-Synchronous Transfer Module-1)数据的接入、串并转换、HDLC(High-level Data Link Control)解帧等功能,完成32路64K信令的并发处理,模块运行状态可查可看,达到了预期的效果。以STM-1为例,基于现有功能的模块化设计,可以平滑地扩展到STM-4、STM-16的应用。
