基于FPGAs的智能机器人导航系统

现场可编程门阵列(FPGAs)是超大规模可编程专用集成电路,进化算法是能够在线自适应的硬件,它包括进化系统、遗传算法和遗传编程,算法从生物学上求解待定问题的计算方法得到灵感。给出一种基于FPGAs 的新的进化算法,算法中的种群由联想种群和改进种群两个子种群组成且可动态地可重配置,对改进种群中的每个染色体都使用复制、变异和选择操作,不对联想种群而只对改进种群进行变异操作,算法成功地导航机器人在复杂变化的环境中实现避碰。

Fault Tolerant Design of Large-Scale Digital Beam Forming in SRAM-FPGAs for Software Defined Satellite Platforms

Large scale digital beamforming(LS-DBFs)are widely used in satellite communications for spectrum reuse and transmission enhancement.SRAM-FPGAs are a popular option for software defined satellite platforms due to their rich computation resources and high flexibility.However,they are sensitive to soft errors,which limit their application in space.This paper discusses the application of coding based fault tolerance schemes for the protection of LS-DBFs on software defined payloads.Since multiple FPGAs are usually needed to support the whole LS-DBFs system,different decomposition schemes are compared in terms of resource efficiency and reliability when the coding based scheme is applied to protect the DBFs on a FPGA.Theoretical analysis and hardware experiments shows that resource efficiency and reliability are a pair of contradictory requirements for decomposition schemes.The protection with vertical decomposition could improve the reliability by 96%with 1.5x redundancy.And the protection with horizontal decomposition could improve the reliability by 85%with 1.2 x redundancy.

Heavy ion‑induced MCUs in 28nm SRAM‑based FPGAs:upset proportions,classifications,and pattern shapes

For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide the actual MCU response of devices and proposing an effective MCU distinction method are urgently needed.In this study,high-and medium-energy heavy-ion irradiations for the configuration random-access memory of 28 nm FPGAs are performed.An MCU extraction method supported by theoretical predictions is proposed to study the MCU sizes,shapes,and frequencies in detail.Based on the extraction method,the different percentages,and orientations of the large MCUs in both the azimuth and zenith directions determine the worse irradiation response of the FPGAs.The extracted largest 9-bit MCUs indicate that high-energy heavy ions can induce more severe failures than medium-energy ones.The results show that both the use of high-energy heavy ions during MCU evaluations and effective protection for the application of high-density 28 nm FPGAs in space are extremely necessary.

Accurate Interconnection Length and Routing Channel Width Estimates for FPGAs

We study the problem of the prediction of interconnection dimensions for FPGAs, including estimating interconnection length and channel width. Experimental results show that our estimates are more accurate than those of existing methods.

最先进的10万门现场可编程门阵列(FPGAs)

本文介绍了国际上最新的10万门FPGA系列，该产品由美国GateField公司研制，采用Flash存储器作为控制码存储单元以及一种和掩膜式门阵列类似的“细粒”可编程逻辑单元，其单元面积大大小于现在市场上的SRAM结构和EPROM结构的FPGA及EPLD单元，目前采用0．8μm工艺已达10万门高密度。本文对其多层次“瓦片”式结构也作了较详细介绍。

FPGAs——支持DSP技术在实时视频处理中的应用

实时视频处理对系统级性能提出了极高的要求,几乎最简单的功能也超出了单个通用DSP器件的处理能力。采用可编程逻辑器件进行设计使工程师可利用并行处理技术实现视频信号处理算法。

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS

Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been provided.In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA.The proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is minimized.All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA.Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.

灵活性，自动化中FPGAs一体化的关键

根据National InstrumentsCorp公司（其是总部在美国德克萨斯州奥斯汀的自动化产品供应商）的LabView研发小组经理MikeTrirnbom的说法“FPGA技术赋予了专属硬件线路可靠性、完全并行执行以及快速闭环控制的特性”

Optimization of Global Signal Networks for Island-Style FPGAs

We present a staggered buffer connection method that provides flexibility for buffer insertion while designing global signal networks using the tile-based FPGA design methodology. An exhaustive algorithm is used to analyze the trade-off between area and speed of the global signal networks for this staggered buffer insertion scheme, and the criterion for determining the design parameters is presented. The comparative analytic result shows that the methods in this paper are proven to be more efficient for FPGAs with a large array size.

Experimental study on heavy ion single-event effects in flash-based FPGAs

With extensive use of flash-based field-programmable gate arrays(FPGAs) in military and aerospace applications, single-event effects(SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi Pro ASIC3 product family. The relation between the cross section and different linear energy transfer(LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 →1 upsets(zeros) and 1 →0 upsets(ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 Me V cm2/mg.Post-beam tests show that the programming module is damaged due to the high-LET ions.

Differences in MBUs induced by high-energy and medium-energy heavy ions in 28 nm FPGAs

Multiple-bit upsets(MBUs)have become a threat to modern advanced field-programmable gate arrays(FPGAs)applications in radiation environments.Hence,many investigations have been conducted using mediumenergy heavy ions to study the effects of MBU radiation.However,high-energy heavy ions(HEHIs)greatly affect the size and percentage of MBUs because their ionizationtrack structures differ from those of medium-energy heavy ions.In this study,the different impacts of high-energy and medium-energy heavy ions on MBUs in 28 nm FPGAs as well as their mechanisms are thoroughly investigated.With the Geant4 calculation,more serious energy effects of HEHIs on MBU scales were successfully demonstrated.In addition,we identified worse MBU responses resulting from lowered voltages.The MBU orientation effect was observed in the radiation of different dimensions.The broadened ionization tracks for tilted tests in different dimensions could result in different MBU sizes.The results also revealed that the ionization tracks of tilted HEHIs have more severe impacts on the MBU scales than mediumenergy heavy ions with much higher linear energy transfer.Therefore,comprehensive radiation with HEHIs is indispensable for effective hardened designs to apply highdensity 28 nm FPGAs in deep space exploration.

Test of an ME Chip Based on FPGAs

The characteristic of FPGA, motion estimation(ME) and the full search block matching arithmetic were introduced, it analyses the collectivity configuration of basic working flow in ME. Based on FPGA, the study concentrates on the control, computing and test part of ME chip implementation. In the end PCB of ME chip is designed and completed. ME is an important link of MPEG standard on picture compression, whose characteristics is its huge amount of data and computing task. So people often use special chip to meet the requirement, but there is still not such production in China at present.

Comparative Performance Evaluation of Large FPGAs with CNFET-and CMOS-based Switches in Nanoscale

Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.

A method to improve PUF reliability in FPGAs

Due to the impact of voltage,temperature and device aging,the traditional ring oscillator-based physical unclonable functions(RO-PUF)suffers from a unreliability issue,i.e.,PUF output is subject to a constant change.To improve the reliability of the PUF,a stability test scheme related to the PUF mapping unit is proposed.The scheme uses ring oscillators with multiple complexity and various frequencies as sources of interference,which are placed near the PUF prototype circuit to interfere with it.By identifying and discarding unstable slices whichlead to t e instability of PUF,PUF reliability can be effectively improved.Experimental results show that surrounding logic circuits with multiple complexity and multiple frequencies can identify different unstable slices,a d the higher the complexity,t e more unstable slices are detected.Moreover,compared with newly published PUF literature,t e PUF cicuit possesses better statistical characteristic of randomness and lower resource consumption.W it temperatures varying from 0 to 120 t and voltage fluctuating between 0.85 and 1.2 V,its uniqueness and stability can achieve 49.78%a d 98.00%,respectively,which makes it better for use in t e field of security.

Low complexity SEU mitigation technique for SRAM-based FPGAs

An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.

QuickLogic宣布低功耗FPGAs时代来临

嵌入式标准产品(ESP)的先驱企业QuickLogic公司日前宣布低功耗FPGAs时代已经来临，使用QuickWorks 9．6版开发软件，ViaLink金属对金属(metal-to-metal)专利互连技术，QuickLogic开发的Eclipse Ⅱ产品系列为设计FPGA、CPLD、DSP和ASIC的工程师们提供了多重选择，上述应用都要求超低功耗、小型封装以及针对设计IP窃取和逆向工程的安全保护。

Dynamic power-gating for leakage power reduction in FPGAs

Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability.In battery-restricted applications such as handheld electronics systems,low-power FPGAs are in great demand.Leakage power almost equals dynamic power in modern integrated circuit technologies,so the reduction of leakage power leads to significant energy savings.We propose a power-efficient architecture for static random access memory(SRAM) based FPGAs,in which two modes (active mode and sleep mode) are defined for each module.In sleep mode,ultralow leakage power is consumed by the module.The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors.After producing the correct outputs,the module returns to sleep mode.The proposed circuit design reduces the leakage power consumption in both active and sleep modes.The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina(MCNC) benchmark circuits on FPGA-SPICE software.Simulation results show an approximately 95%reduction in leakage power consumption in sleep mode.Moreover,the total power consumption (leakage+dynamic power consumption) is reduced by more than 15%compared with that of the best previous design.The average area overhead (4.26%) is less than those of other powergating designs.

同步辐射装置主信号源的扩展方法研究

主信号源是同步辐射装置的关键组成部分之一,它不仅用于产生同步辐射光源各子系统所需的稳定度极高的参考信号,还用于生成整个装置的控制系统所需的高精度工作时钟。一般使用射频信号源作为主信号源,而商业射频信号源一般只配备单输出通道,远远不能满足同步辐射装置的需要,使用传统功分器对主信号通道进行扩展又存在幅度衰减、精度下降且相位不一致的问题。为解决上述问题,利用射频芯片AD9361,研究了对主信号源的单路输出进行扩展的方法。该方法可根据用户需求完成相应数量的信号通道扩展,设计了AD9361芯片和FPGA主控模块相结合的硬件架构。搭建实验平台,开展了射频信号源在C波段扩展的实验研究,对所提出的扩展方法进行实验验证。实验结果表明,该方法能保证扩展信号的幅度、频率与相位与主信号保持高度一致。

国产FPGA上通信基带发端算法设计和系统实现

该文针对国产FPGA上通信基带算法及相关信号处理算法IP核匮乏现状,设计了基于紫光Logos系列FPGA器件的通信基带发端算法;在紫光FPGA缺乏FIR IP核的情况下,经优化设计实现了仅用7个乘法器的60阶FIR成型滤波器;搭建收发测试环境对设计的发端系统进行了测试。测试结果表明,所设计的基于正交调制的发端基带算法和基带系统性能达到主流水平的技术指标要求,实现了首批通信算法和通信系统在国产FPGA器件上的应用。