Fault injection system for automatic testing system

Considering the deficiency of the means for confirming the attribution of fault redundancy in the re-search of Automatic Testing System(ATS) , a fault-injection system has been proposed to study fault redundancyof automatic testing system through compurison. By means of a fault-imbeded environmental simulation, thefaults injected at the input level of the software are under test. These faults may induce inherent failure mode,thus bringing about unexpected output, and the anticipated goal of the test is attained. The fault injection con-sists of voltage signal generator, current signal generator and rear drive circuit which are specially developed,and the ATS can work regularly by means of software simulation. The experimental results indicate that the faultinjection system can find the deficiency of the automatic testing software, and identify the preference of fault re-dundancy. On the other hand, some soft deficiency never exposed before can be identified by analyzing the tes-ting results.

A fault injection model-oriented testing strategy for component security

A fault injection model-oriented testing strategy was proposed for detecting component vulnerabilities.A fault injection model was defined,and the faults were injected into the tested component based on the fault injection model to trigger security exceptions.The testing process could be recorded by the monitoring mechanism of the strategy,and the monitoring information was written into the security log.The component vulnerabilities could be detected by the detecting algorithm through analyzing the security log.Lastly,some experiments were done in an integration testing platform to verify the applicability of the strategy.The experimental results show that the strategy is effective and operable.The detecting rate is more than 90%for vulnerability components.

Study of fault injection system based on software

A software fault injection system SFIS is designed,which consists of the target system plus a fault injector,fault library,workload,data collector,and data analyzer. A serial communication mechanism is adopted to simulate the factual work environment. Then a fault model is built for single particle event,which can be denoted as FM=(FL,FT). FL stands for fault location,and FT stands for fault type. The fault model supports three temporal faults: transient,intermittent,and permanent. During the experiments implemented by SFIS,the software interruption method is adopted to inject transient faults,and step trace method is adopted to inject permanent faults into the target system. The experiment results indicate that for the injected transient code segment faults,2.8 % of them do not affect the program output,80.1% of them are detected by the built-in error detection in the system,and 17.1% of them are not detected by fault detection mechanism. The experiment results verify the validity of the fault injection method.

Single event effects evaluation on convolution neural network in Xilinx 28 nm system on chip

Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects(SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm systemon-chip(SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.

An Improved Differential Fault Analysis on Block Cipher KLEIN-64

KLEIN-64 is a lightweight block cipher designed for resource-constrained environment,and it has advantages in software performance and hardware implementation.Recent investigation shows that KLEIN-64 is vulnerable to differential fault attack(DFA).In this paper,an improved DFA is performed to KLEIN-64.It is found that the differential propagation path and the distribution of the S-box can be fully utilized to distinguish the correct and wrong keys when a half-byte fault is injected in the 10th round.By analyzing the difference matrix before the last round of S-box,the location of fault injection can be limited to a small range.Thus,this improved analysis can greatly improve the attack efficiency.For the best case,the scale of brute-force attack is only 256.While for the worst case,the scale of brute-force attack is far less than 232 with another half byte fault injection,and the probability for this case is 1/64.Furthermore,the measures for KLEIN-64 in resisting the improved DFA are proposed.

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS

Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system electronics.However,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been provided.In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA.The proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is minimized.All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA.Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.

Diesel Engine Fault Diagnosis with Vibration Signal

When the vibration of diesel engine structure is measured, the signal is composed of a very complex superposition of the contributions of different vibratory sources modified by their respective transmission paths. These sources originate from several internal phenomenon in the engine such as combustion pressure variation, unbalanced reciprocating and rotating parts. In a diesel engine, movement parts work in a specific order. Once the starting point is determined, occurrence of work order in different cycle phases can be determined. This could successfully use to identifying of impulses in complex vibration signal of a diesel engine. From the variation of features of those impulses, it is possible to determine the working condition of the engine. This can use to fault diagnosis of diesel engine, specially faults related to combustion process.

A Secure Hardware Implementation for Elliptic Curve Digital Signature Algorithm

Since the end of the 1990s,cryptosystems implemented on smart cards have had to deal with two main categories of attacks:side-channel attacks and fault injection attacks.Countermeasures have been developed and validated against these two types of attacks,taking into account a well-defined attacker model.This work focuses on small vulnerabilities and countermeasures related to the Elliptic Curve Digital Signature Algorithm(ECDSA)algorithm.The work done in this paper focuses on protecting the ECDSA algorithm against fault-injection attacks.More precisely,we are interested in the countermeasures of scalar multiplication in the body of the elliptic curves to protect against attacks concerning only a few bits of secret may be sufficient to recover the private key.ECDSA can be implemented in different ways,in software or via dedicated hardware or a mix of both.Many different architectures are therefore possible to implement an ECDSA-based system.For this reason,this work focuses mainly on the hardware implementation of the digital signature ECDSA.In addition,the proposed ECDSA architecture with and without fault detection for the scalar multiplication have been implemented on Xilinxfield programmable gate arrays(FPGA)platform(Virtex-5).Our implementation results have been compared and discussed.Our area,frequency,area overhead and frequency degradation have been compared and it is shown that the proposed architecture of ECDSA with fault detection for the scalar multiplication allows a trade-off between the hardware overhead and the security of the ECDSA.

Method of militarysoftware securityand vulnerability testing based on process mutation

To solve the problems caused by military software security issues,this paper firstly introduces a new software fault injection technique,namely main static fault injection method:program mutation.And then source code for testing this algorithm is put forward.On this basis buffer overflow testing based on program mutation is conducted.Finally several military software source codes for buffer overflow testing are tested using deficiency tracking system(DTS)tool,Experimental results show the effectiveness of the proposed algorithm.

Review of Model-Based Testing Approaches in Production Automation and Adjacent Domains—Current Challenges and Research Gaps

As production automation systems have been and are becoming more and more complex, the task of quality assurance is increasingly challenging. Model-based testing is a research field addressing this challenge and many approaches have been suggested for different applications. The goal of this paper is to review these approaches regarding their suitability for the domain of production automation in order to identify current trends and research gaps. The different approaches are classified and clustered according to their main focus which is either testing and test case generation from some form of model automatons, test case generation from models used within the development process of production automation systems, test case generation from fault models or test case selection and regression testing.

Finds in Testing Experiments for Model Evaluation

To evaluate the fault location and the failure prediction models, simulation-based and code- based experiments were conducted to collect the required failure data. The PIE model was applied to simu- late failures in the simulation-based experiment. Based on syntax and semantic level fault injections, a hy- brid fault injection model is presented. To analyze the injected faults, the difficulty to inject (DTI) and diffi- culty to detect (DTD) are introduced and are measured from the programs used in the code-based experi- ment. Three interesting results were obtained from the experiments: 1) Failures simulated by the PIE model without consideration of the program and testing features are unreliably predicted; 2) There is no obvious correlation between the DTI and DTD parameters; 3) The DTD for syntax level faults changes in a different pattern to that for semantic level faults when the DTI increases. The results show that the parameters have a strong effect on the failures simulated, and the measurement of DTD is not strict.

An SEU-hardened latch with a triple-interlocked structure

A single event upset （SEU） tolerant latch with a triple-interlocked structure is presented. Its self-recovery mechanism is implemented by using three pairs of guard-gates and inverters to construct feedback lines inside the structure. This latch effectively suppresses the effects of charge deposition at any single internal node caused by particle strikes. Three recently reported SEU-hardened latches are chosen and compared with this latch in terms of reliability. The potential problems that these three latches could still get flipped due to single event effects or single event effects plus crosstalk coupling are pointed out, which can be mitigated by this proposed latch. The SEU tolerance of each latch design is evaluated through circuit-level SEU injection simulation. Furthermore, discussions on the crosstalk robustness and some other characteristics of these latches are also presented.

A software solution to estimate the SEU-induced soft error rate for systems implemented on SRAM-based FPGAs

SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets （SEUs） in space applications. The failure mechanism in FPGA＇s configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.