An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv...An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.展开更多
We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify ...We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify the chaos properties of this system, the existence of horseshoe in the four-wing attractor is presented. Firstly, a Poincar6 section is selected properly, and a first-return Poincar6 map is established. Then, a one-dimensional tensile horseshoe is discovered, which verifies the chaos existence of the system in mathematical view. Finally, the fractional-order chaotic attractor is imple- mented physically with a field-programmable gate array (FPGA) chip, which is useful in further engineering applications of information encryption and secure communications.展开更多
This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)fu...This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.展开更多
移动终端通过小区搜索完成与网络的接入工作。为了更快地完成时分长期演进(time division long term evolution,TD-LTE)系统小区搜索过程,与传统数字信号处理(digital signal processing,DSP)串行模式对比,从速度和面积两方面综合考虑,...移动终端通过小区搜索完成与网络的接入工作。为了更快地完成时分长期演进(time division long term evolution,TD-LTE)系统小区搜索过程,与传统数字信号处理(digital signal processing,DSP)串行模式对比,从速度和面积两方面综合考虑,提出一种基于现场可编程门阵列(field programmable gate array,FPGA)的多通道并行小区搜索架构。主要工作集中在小区搜索整体方案设计和FPGA硬件实现上,在算法上对整个小区搜索算法架构进行了改进,同时根据硬件需求,利用以时钟换取速度的思想对FPGA硬件实现架构进行了优化。采用多通道并行高速乘法器进行序列相关检测和动态门限配置的方法,大大缩短了TD-LTE小区搜索的处理时间。并以Altera的EP4SGX230KF40C2芯片作为硬件平台进行了Modelsim功能仿真、板级验证等工作。实验结果表明,该设计方案的处理速度和数据精度均满足TD-LTE系统测试要求,性能远优于传统的DSP架构模式,可以应用到实际工程中。展开更多
给出了嵌入式GPS接收机系统的整体设计,重点研究了系统中FPGA的不同配置方法,提出了利用CPLD和Platform Flash、SPI Flash、Intel NOR Flash实现对FPGA进行不同配置的方法,详细分析了每种配置方法的特点,给出具体的硬件电路设计,并重点...给出了嵌入式GPS接收机系统的整体设计,重点研究了系统中FPGA的不同配置方法,提出了利用CPLD和Platform Flash、SPI Flash、Intel NOR Flash实现对FPGA进行不同配置的方法,详细分析了每种配置方法的特点,给出具体的硬件电路设计,并重点研究了利用Intel NOR Flash进行BPI配置的流程以及配置时应注意的问题。这些配置方式在研究的嵌入式GPS接收机系统中得到了成功的应用,而且也适用于其他的类似系统。展开更多
文摘An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61502340 and 61374169)the Application Base and Frontier Technology Research Project of Tianjin,China(Grant No.15JCYBJC51800)the South African National Research Foundation Incentive Grants(Grant No.81705)
文摘We present a fractional-order three-dimensional chaotic system, which can generate four-wing chaotic attractor. Dy- namics of the fractional-order system is investigated by numerical simulations. To rigorously verify the chaos properties of this system, the existence of horseshoe in the four-wing attractor is presented. Firstly, a Poincar6 section is selected properly, and a first-return Poincar6 map is established. Then, a one-dimensional tensile horseshoe is discovered, which verifies the chaos existence of the system in mathematical view. Finally, the fractional-order chaotic attractor is imple- mented physically with a field-programmable gate array (FPGA) chip, which is useful in further engineering applications of information encryption and secure communications.
基金supported by the National Natural Science Foundation of China(No.62174150)the Natural Science Foundation of Jiangsu Province,China(Nos.BK20211040 and BK20211041)。
文摘This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.
文摘移动终端通过小区搜索完成与网络的接入工作。为了更快地完成时分长期演进(time division long term evolution,TD-LTE)系统小区搜索过程,与传统数字信号处理(digital signal processing,DSP)串行模式对比,从速度和面积两方面综合考虑,提出一种基于现场可编程门阵列(field programmable gate array,FPGA)的多通道并行小区搜索架构。主要工作集中在小区搜索整体方案设计和FPGA硬件实现上,在算法上对整个小区搜索算法架构进行了改进,同时根据硬件需求,利用以时钟换取速度的思想对FPGA硬件实现架构进行了优化。采用多通道并行高速乘法器进行序列相关检测和动态门限配置的方法,大大缩短了TD-LTE小区搜索的处理时间。并以Altera的EP4SGX230KF40C2芯片作为硬件平台进行了Modelsim功能仿真、板级验证等工作。实验结果表明,该设计方案的处理速度和数据精度均满足TD-LTE系统测试要求,性能远优于传统的DSP架构模式,可以应用到实际工程中。
文摘给出了嵌入式GPS接收机系统的整体设计,重点研究了系统中FPGA的不同配置方法,提出了利用CPLD和Platform Flash、SPI Flash、Intel NOR Flash实现对FPGA进行不同配置的方法,详细分析了每种配置方法的特点,给出具体的硬件电路设计,并重点研究了利用Intel NOR Flash进行BPI配置的流程以及配置时应注意的问题。这些配置方式在研究的嵌入式GPS接收机系统中得到了成功的应用,而且也适用于其他的类似系统。