A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA)

In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.

Synthesis of Nonlinear Control of Switching Topologies of Buck-Boost Converter Using Fuzzy Logic on Field Programmable Gate Array (FPGA)

An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.

Fault Prediction and Diagnosis of Warship Equipment Field Programmable Gate Array Software

In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.

GJB 5000B在FPGA工程中的应用分析

为引入软件工程化管理办法对设计开发实践实施管理,结合GJB 5000B体系要求,对现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的设计开发流程和GJB 5000B的工程实践要求进行梳理、比对和分析,并提出一套FPGA开发管理在GJB 5000B推进实践中的实施办法。研究成果可为GJB 5000B在FPGA工程中的应用提供一定参考。

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

基于DSP与FPGA的变流器通用控制平台研究

提出一种基于DSP和现场可编程门阵列(FPGA)双CPU结构的新型变流器控制系统方案,其中DSP完成变流器控制策略的实现,主要包括:最大功率点跟踪、电压电流双闭环控制、低电压穿越控制、通信功能;FPGA完成三相锁相环控制、AD芯片采样控制、SVPWM波形控制、逻辑输出控制以及各类故障信号检测与停机保护功能,并采用了基于WIFI模块的风电故障信息传输系统。以双馈风电变流器为模型,设计了双馈风力发电变流器系统,完成了两电平与三电平SVPWM控制算法的FPGA实现。最后在自主研发的1.5 MW,2 MW双馈式变流器样机与光伏逆变器样机上进行了大量实验和长期的现场试运行,验证了控制系统平台的可行性与实用性。

SRAM型FPGA单粒子辐照试验系统技术研究

单粒子辐射效应严重制约FPGA的空间应用,为提高FPGA在辐射环境中的可靠性,深入研究抗辐射加固FPGA单粒子效应评估方法,设计优化单粒子效应评估方案,开发相应的评估系统,提出基于SRAM时序修正的码流存储比较技术和基于SelectMAP端口配置回读技术。借助国内高能量大注量率的辐照试验环境,完成FPGA单粒子翻转(SEU)、单粒子闩锁(SEL)和单粒子功能中断(SEFI)等单粒子效应的检测,试验结果表明,该方法可以科学有效地对SRAM型FPGA抗单粒子辐射性能进行评估。

基于FPGA弱小信号测量系统研究与实现

在信号测量领域,弱小信号测量应用非常广泛,但是弱小信号测量存在误差大的问题,为了解这个问题,文章提出了基于FPGA弱小信号测量系统,FPGA具有集成度高、速度快的优点,FPGA是整个测量系统的控制核心。通过FPGA内部资源实现了数字锁相放大器,这样测量信号就不受运放温漂和偏置影响;通过光耦隔离电路、二阶低通滤波器有效的提高电压信号测量的稳定性。此系统结构简单、功耗低、扩展灵活同时还可以实现在线升级。文章对测试的数据使用最小二乘法拟合曲线进行了误差分析,测试和分析的结果表明,此系统测量精度高,可以达到0.93%,能很好的应用在微弱信号测量中领域。

阻塞斩波三相交交变频电源的FPGA控制实现

变频技术是重要的节能技术,所以针对低频或转速不恒定的节能设备,提出了基于FPGA数字控制的三相交交直接变频电源技术。用VHDL语言对主控芯片FPGA编写程序,其输出的高频SPWM信号经驱动电路后作为电源和负载间开关MOSFET的控制信号。MOSFET周期性地部分阻塞电源不能达到负载来改变输出电压的频率,同时在放行的时区斩波来改变输出电压的幅值。基于Matlab仿真平台,对系统进行了建模和仿真,仿真结果验证了该技术的正确性。最后给出了频率为7.14 Hz和2.63 Hz的实验波形,实验结果证明了该技术的可行性。

基于FPGA的连续相位π/4DQPSK调制器和解调器

以FPGA器件为核心设计连续相位π/4DQPSK的调制器和解调器 ,将绝大部分功能模块由大规模FPGA内部资源来实现 ,这样既可以提高通信系统的稳定性和灵活性 ,又便于系统的集成化和小型化 .由于连续相位π/4DQPSK调制独特的相位变化 ,调制器中采用了双通道设计 ,成功实现了过渡区相位与主要区间相位的交替产生 .解调器中利用计数器控制抽样时刻 ,保证抽取出的信号值处于码元的主要区间 .

10 Gbit/s PRBS tester implemented in FPGA

The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.

Design of IP core for IIC bus controller based on FPGA

The intellectual property （IP） core for inter-integrated circuit （IIC） bus controller is designed using finite state machine （FSM） based on field programmable gate array （FPGA）. Not only the data from AT 24C02C can be read automatically after power on, but also the data from upper computer can be written into AT24C02C immediately under the control of the IIC bus controller. When it is applied to blast wave overpressure test system, the IIC bus controller can read and store working parameters automatically. In a laboratory environment, the IP core simulation is carried out and the result is accurate. In the explosion field test, by analyzing the obtained valid data, it can be concluded that the designed IP core has good reliability.

FPGA implementation of bit-stream neuron and perceptron based on sigma delta modulation

To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.

大尺寸机载显示模块动态背光控制系统设计

机载大尺寸液晶显示器(liquid crystal display,LCD)显示模块具有亮度高和功耗大的特点。为了降低其动态功耗,介绍了一种用于大尺寸机载显示模块的动态背光控制系统。该系统采用发光二极管(light emitting diode,LED)动态背光控制技术,通过对背光的动态调节,提高动态显示效果和达到节能的目的。对系统的硬件电路和软件设计算法进行了详细的介绍,并进行实验验证。结果表明,该系统能够有效地提高机载显示模块的动态显示效果,并显著降低了动态功耗。

Mosaic line-scan camera based on FPGA

Because single line-scan camera loses light in the edge of the sensor when the field of view is large, a mosaic cam- era based on field programmable gate array （FPGA） is presented by putting multiple cameras arranged in a straight line to share the field of view and reduce the view angle of every camera. For detecting doping micro particles with the designed mosaic line-scan camera, a detection algorithm of the target＇s location in FPGA is proposed. Finally, the practicability and stability of the system were validated experimentally. The results of the experiment show that the camera can get images clearly with less light loss and can accurately distinguish the target and the background.

IPSec安全网卡上消息认证模块的FPGA实现

首先对IPSec安全网卡的整体框架,以及其中的IPSec模块和消息认证模块的结构框图作简要介绍,然后详细阐述了常用消息认证算法HMAC-MD5和HMAC-SHA1的硬件实现,得到综合与仿真的结果。最后通过对两个算法实现的分析比较,总结出提高运行速度的方法。

GPS P码接收机本地信号发生器的FPGA实现

P码作为GPS军用伪码,具有结构复杂、周期长且码速率快的特点,这使得使用P码的软件接收机不仅定位精度高,且具有很强的抗干扰和反欺骗能力。能够实现任意卫星的任意时刻P码的产生,对于实现P码直接捕获和跟踪有很重要的意义。对于P码的产生原理和结构进行了分析,基于MATLAB设计了相应的P码发生算法并进行简单的算法仿真。之后针对FPGA硬件平台对P码发生器进行了相应的模块设计,包含寄存器模块、延时模块、周期控制模块和寄存器相位模块等。测试实验结果表明P码发生器可以基本无延迟地生成任意卫星、任意时刻的P码。

Design of IRIG-B(AC) encoder based on FPGA

InterRange Instrumentation Group（IRIG-B（AC））code is usually used in the shooting range test for time information transmission and systems time synchronization.According to IRIG-B（AC）code format and modulation principle,this paper presents IRIG-B（AC）coding circuit design scheme based on field programmable gate array（FPGA）.The B（AC）code signal is generated by AD7245,a digital-to-analog（D/A）converter.After amplified,the signal can be used directly for system time synchronization,and the amplitude of the signal can be adjusted according to different requirements.The IRIG-B（AC）encoder designed has been verified by test.The test results show that it can output accurate time information and has higher practicality.

基于FPGA的控制算法定点化设计

运动控制算法在现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)上实现过程中,当数据类型由浮点转定点时,存在无法保证高精度的问题。为此使用simulink中的定点工具(Fixed-Point Tool)对算法内部各信号数据的范围进行分析,然后人为地对Fixed-Point Tool给出的建议位宽进行修正,从而使算法在保证较高精度的同时,也解决了采用统一较长位宽在FPGA上实现时造成的资源浪费问题。与传统的人为定义数据位宽相比,使用Fixed-Point Tool设置数据位宽,在输入数据范围发生变化时,能够更加灵活、动态地调整算法内部数据位宽。