Design Consideration in the Development of Multi-Fin FETs for RF Applications

In this paper, we propose multi-fin FET design techniques targeted for RF applications. Overlap and underlap design configuration in a base FinFET are compared first and then multi-fin device (consisting of transistor unit up to 50) is studied to develop design limitations and to evaluate their effects on the device performance. We have also investigated the impact of the number of fins (up to 50) in multi-fin structure and resulting RF parameters. Our results show that as the number of fin increases, underlap design compromises RF performance and short channel effects. The results provide technical understanding that is necessary to realize new opportunities for RF and analog mixed-signal design with nanoscale FinFETs.

4H-SiC基FinFET器件的单粒子瞬态效应研究

深入分析新结构、新材料的单粒子瞬态(SET)效应机理是开展抗辐射加固设计的基础和前提。基于Si基14 nm SOI Fin FET器件,构建了4H-Si C基的SET仿真模型。对比分析了不同Fin材料、不同粒子能量对4H-Si C基Fin FET器件SET的影响机理。结果表明,与Si材料相比,4H-Si C材料具有宽禁带的特点和较高的复合率,在高能粒子入射时形成的SET脉冲更小,其瞬态电流峰值及收集电荷量相对Si材料分别下降了79.64%和83.35%,且随着粒子能量的增加,两者与Si材料的差值均呈幂指数增加。

Line-edge roughness induced single event transient variation in SOI Fin FETs

The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When Fin FET biased at OFF state configuration（Vgs D0, Vds DVdd/ is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse（single event transient, SET） is consequently formed. The results reveal that with the presence of line-edge roughness（LER）, which is one of the major variation sources in nano-scale Fin FETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered： type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters,correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.

FinFET静电可靠性及新型Fix-base SOI FinFET研究

在鳍型场效应晶体管(SOI FinFET)相关静电防护技术研究基础上,提出了一种新型的体区接触固定型绝缘体上硅鳍型场效应晶体管泄放钳位装置(Fix-base SOI FinFET Clamp)。该新型结构的器件解决了基区接触浮空在静电防护设计时引起的一系列问题,而且对正常的FinFET工艺具有良好的兼容性。通过计算机辅助工艺设计(TCAD)仿真论证了Fix-base SOI FinFET Clamp具有明显效果,详细阐述和讨论了SOI FinFET和Fix-base SOI FinFET Clamp工作状态下的电流和热分布。

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient(SET)pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor(Fin FET)inverter chains with different driven strengths are measured at different temperatures.Three-dimensional(3D)technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature.Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk Fin FET technology,resulting in the increase of SET pulse width.On the other hand,the increase of inverter driven strength will change the layout topology,which has a complex influence on the SET temperature effects of Fin FET inverter chains.The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

新结构MOSFET

和传统平面结构MOSFET相比,新结构MOSFET具有更好的性能(如改善的沟道效应(SCE),理想的漏诱生势垒降低效应(DIBL)和亚阈值特性)和更大的驱动电流等。文章主要介绍了五种典型的新结构MOSFET,包括平面双栅MOSFET、FinFET、三栅MOSFET、环形栅MOSFET和竖直结构MOSFET。随着MOSFET向亚50nm等比例缩小,这些新结构器件将大有前途。

纳米FinFET器件的单粒子效应研究(英文)

Fin FET器件比主流CMOS技术表现出更多优势,如快速、高集成度、低功耗、多功能性和强扩展性,基于ISE TCAD,考虑迁移率、量子效应、载流子重组、辐射效应等的影响,建立了一种纳米Fin FET器件SEE的3D仿真模型。分析了工艺掺杂浓度、栅压、粒子能量、寄生电容及技术节点等对单粒子瞬态电流的影响,并探讨了其影响机制。基于此分析,找到了一些潜在的工艺加固技术,如降低源极掺杂浓度、增加漏极和衬底的掺杂浓度、减少粒子能量、降低栅压、优化寄生电容等。

三维晶体管和后CMOS器件的进展

2012年当量产的集成电路的特征尺寸进入22 nm时,三维晶体管新结构成为纳电子发展的主流,标志纳电子学的发展由应力Si时代进入三维晶体管时代。介绍了多栅晶体管的发展过程,包括双栅、鳍栅、Pi型栅、Ω型栅、三栅和环形栅等FET关键技术的突破和由于栅极控制沟道电子能力增加而导致的器件性能的改善。同时,还介绍了后CMOS器件的新进展,包含InGaAs n沟道鳍栅FET、环栅纳米线FET、Ge n/p沟道鳍栅FET、碳纳米管FET、石墨烯FET、隧穿FET、单电子晶体管和自旋电子学等,以及后CMOS器件的评定和终结CMOS器件模型。

A transformed analytical model for thermal noise of FinFET based on fringing field approximation

This paper delineates the effect of nonplanar structure of Fin FETs on noise performance. We demonstrate the thermal noise analytical model that has been inferred by taking into account the presence of an additional inverted region in the extended（underlap） S/D region due to finite gate electrode thickness. Noise investigation includes the effects of source drain resistances which become significant as channel length becomes shorter. In this paper, we evaluate the additional noise caused by three dimensional（3-D） structure of the single fin device and then extended analysis of the multi-fin and multi-fingers structure. The addition of fringe field increases its minimum noise figure and noise resistance of approximately 1 d B and 100Ω respectively and optimum admittance increases to 5.45 mΩ at 20 GHz for a device operating under saturation region. Hence, our transformed model plays a significant function in evaluation of accurate noise performance at circuit level.

CMOS工艺节点进展中器件技术的革新

随着CMOS工艺技术的飞速发展,传统MOSFET器件的结构尺寸持续微缩,各种短沟道相关效应对器件性能的影响越来越严峻。在CMOS工艺节点演进中,为了减小短沟道效应的影响,改善器件性能,需要新技术、新材料以及器件结构的革新。文章回顾了应变硅技术、高K电介质、金属栅的应用,并探讨了对传统平面晶体管的器件结构革新,特别是创新的三维器件结构,包括鳍式场效应晶体管FinFET、环绕栅场效应晶体管GAAFET等。分析表明:FinFET结构中,栅极从三面围绕沟道而进行有效控制,可获得较小的亚阈值漏电及低功耗。而GAAFET结构中,栅极环绕沟道具有比FinFET更优异的性能,能够适用于下一代更先进的CMOS工艺节点。

一种源漏缓冲浮栅型低漏电场效应晶体管

为解决当前主流晶体管MOSFET的反向泄漏电流较大的问题,并对传统FINFET做进一步优化,提出一种源漏缓冲浮栅型的具有较低漏电的场效应晶体管。所设计出的双向开关装置具有低静态功耗和低反向泄漏电流,只需一个独立外部供电的栅电极就可控制器件的导通、关断和浮栅擦写功能。通过改变器件中浮栅注入的电荷类型以及半导体中的掺杂浓度,即可使器件工作在不同的模式下,还可使整个器件拥有更低的反向漏电流和更高的正向导通电流。整体结构相互对称,源漏可以互换,因此具有更好的兼容性。

Drive current of accumulation-mode p-channel SOI-based wrap-gated Fin-FETs

Comparisons are performed to study the drive current of accumulation-mode（AM） p-channel wrap-gated Fin-FETs.The drive current of the AM p-channel FET is 15%-26%larger than that of the inversion-mode （IM） p-channel FET with the same wrap-gated fin channel,because of the body current component in the AM FET, which becomes less dominative as the gate overdrive becomes larger.The drive currents of the AM p-channel wrap-gated Fin-FETs are 50%larger than those of the AM p-channel planar FETs,which arises from effective conducting surface broadening and volume accumulation in the AM wrap-gated Fin-FETs.The effective conducting surface broadening is due to wrap-gate-induced multi-surface conduction,while the volume accumulation,namely the majority carrier concentration anywhere in the fin cross section exceeding the fin doping density,is due to the coupling of electric fields from different parts of the wrap gate.Moreover,for AM p-channel wrap-gated Fin-FETs, the current in channel along 110 is larger than that in channel along 100,which arises from the surface mobility difference due to different transport directions and surface orientations.That is more obvious as the gate overdrive becomes larger,when the surface current component plays a more dominative role in the total current.

鳍线场效应管振荡器

研究了几种场效应管（ＦＥＴ）鳍线振荡器，提出一种稳频电路，建立了电路分析模型和计算公式。

Electrical contacts to two-dimensional transition-metal dichalcogenides

Two-dimensional(2D) transition-metal dichalcogenides(TMDCs) have attracted enormous interests as the novel channel materials for atomically thin transistors. Despite considerable progress in recent years, the transistor performance is largely limited by the excessive contact resistance at the source/drain interface. In this review, a summary of recent progress on improving electrical contact to TMDC transistors is presented. Several important strategies including topology of contacts, choice of metals and interface engineering are discussed.