First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implem...First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.展开更多
针对高速数据通信系统中因不同通道的时延差异造成的数据延迟不一致问题,提出一种多通道高速数据对齐的实现方案。通过时钟芯片产生标准的周期可配的基准信号,在发送侧产生同步于基准时钟的采样时钟,在接收侧产生同步于基准时钟的读时钟...针对高速数据通信系统中因不同通道的时延差异造成的数据延迟不一致问题,提出一种多通道高速数据对齐的实现方案。通过时钟芯片产生标准的周期可配的基准信号,在发送侧产生同步于基准时钟的采样时钟,在接收侧产生同步于基准时钟的读时钟,利用采样时钟控制发送侧多通道同时采样,并利用读时钟控制接收侧多通道独立队列的数据读取。将所提方案运用在25 G PON系统中,实验结果表明,该方案能够完成高速通信系统中的多通道数据对齐,且系统有较高的鲁棒性和资源利用率。展开更多
文摘First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.
文摘为满足现代高分辨率雷达大容量高速缓存以及被动雷达和时差定位系统采样预触发的需要,提出了采用多片先进先出(F IFO)芯片级联的硬件结构实现可编程采样预触发和缓存容量扩展.分析了两级F IFO级联时芯片间接口的时序,给出了对F IFO可编程标志位的设置方法.实际应用证明,采用该结构可使系统的缓存容量达到2 M B,预触发量达到1 M B,且两种功能可由FPGA控制切换.该结构也适用于其它具有可编程标志的F IFO.
文摘针对高速数据通信系统中因不同通道的时延差异造成的数据延迟不一致问题,提出一种多通道高速数据对齐的实现方案。通过时钟芯片产生标准的周期可配的基准信号,在发送侧产生同步于基准时钟的采样时钟,在接收侧产生同步于基准时钟的读时钟,利用采样时钟控制发送侧多通道同时采样,并利用读时钟控制接收侧多通道独立队列的数据读取。将所提方案运用在25 G PON系统中,实验结果表明,该方案能够完成高速通信系统中的多通道数据对齐,且系统有较高的鲁棒性和资源利用率。
