Simulation of a Novel Schottky Body-Contacted Structure Suppressing Floating Body Effect in Partially-Depleted SOI nMOSFET's

A novel Schottky body-contacted structure for partially depleted SOI nMOSFET's is presented.This structure can be realized by forming a shallow n +-p junction and two sidewall spacers in the source region,and then growing a thick silicide film,which can punch through the shallow junction and make a Schottky contact to the p-type silicon.Simulation results show that the anomalous subthreshold slope and kink effects are suppressed successfully and the drain breakdown voltage is improved considerably.This method has the same device area and is completely compatible with the bulk MOSFET process.

Floating Body Effect in Partially Depleted SOI nMOSFET with Asymmetric Structure and Ge-Implantation

The floating body effect of an asymmetric and Ge implanted partially depleted 0 8μm SOI nMOSFET is investigated.It is found that the drain breakdown voltage can be improved by about 1V and that the anomalous subthreshold slope and kink effect are also lessened.It is believed that the shallow junction in the source and defect states introduced by Ge implantation are responsible for the reduction of the floating body effect.

Influence of Floating Body Effect on Radiation Hardness of PD SOI nMOSFETs

H-gate and closed-gate PD SOI nMOSFETs are fabricated on SIMOX substrate,and the influence of floating body effect on the radiation hardness is studied.All the subthreshold characteristics of the devices do not change much after radiation of the total dose of 106rad(Si).The back gate threshold voltage shift of closed-gate is about 33% less than that of H-gate device.The reason should be that the body potential of the closed-gate device is raised due to impact ionization,and an electric field is produced across the BOX.The floating body effect can improve the radiation hardness of the back gate transistor.

Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

In this paper, the effect of floating body effect （FBE） on a single event transient generation mechanism in fully depleted （FD） silicon-on-insulator （SOI） technology is investigated using three-dimensional technology computer-aided design （3D- TCAD） numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect （FBE） whether for positive or negative channel metal oxide semiconductor （PMOS or NMOS）. Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking （IS） layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.

Body-contact self-bias effect in partially depleted SOI-CMOS and alternatives to suppress floating body effect

As SOI-CMOS technology nodes reach the tens ofnanometer regime, body-contacts become more and more ineffective to suppress the floating body effect. In this paper, self-bias effect as the cause for this failure is analyzed and discussed in depth with respect to different structures and conditions. Other alternative approaches to suppressing the floating body effect are also introduced and discussed.

Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.

Gate-to-body tunneling current model for silicon-on-insulator MOSFETs

A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.

Eliminating the floating-body effects in a novel CMOS-compatible thin-SOI LDMOS

A novel CMOS-compatible thin film SOI LDMOS with a novel body contact structure is proposed. It has a Si window and a P-body extended to the substrate through the Si window, thus, the P-body touches the P＋ region to form the body contact. Compared with the conventional floating body SOI LDMOS （FB SOI LDMOS） structure, the new structure increases the off-state BV by 54%, decreases the specific on resistance by 20%, improves the output characteristics significantly, and suppresses the self-heating effect. Furthermore, the advantages of the low leakage current and low output capacitance of SOI devices do not degrade.

A Novel LDMOS Structure in Thin Film Patterned-SOI Technology with a Silicon Window Beneath p Well

A novel patterned-SOI LDMOS structure with a silicon window beneath the p well is proposed.The performance is simulated numerically.In comparison to SOI counterpart,the off-state and the on-state breakdown voltage can increase by 57% and 70% respectively;transconductance is flatter;I-V curves take no sign of kink in the saturation region;the device temperature is much lower even at high input power;the floating body effect and the self-heating effect are distinctly suppressed.Furthermore,the advantage of low leakage current and low output capacitance in SOI structures does not degrade.The proposed structure will be a promising choice to improve the performance and reliability of SOI power device.