Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.

New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits

New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

A Novel Design of Octal-Valued Logic Full Adder Using Light Color State Model

Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area.This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing.We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model.Four case studies were used to assure the validity of the proposed adder.These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.

Study and Evaluation in CMOS Full Adders

Low power adder circuits, SERF, 10T Ⅰ,10T Ⅱ,10T Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circuit setups can impact the speed and power consumption. In addition, impacts of output inverters on the circuit performance of modified SERF and 10T adders due to threshold loss problem are also examined. Differences among these adders are addressed and applications of these adders are suggested.

Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry-Save Adder for Digital FIR Filter

Improvement of digital FIR filter is vital in the field of Digital Signal Processing in order to reduce the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite Impulse Response (FIR) filter has been designed using efficient multiplier and adder circuits for optimized APT (Area,Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. These compact full adder and half adder structures are incorporated into Wallace Multiplier and Improved Carry-Save Adder. The proposed 16-bit Carry-Save Adder has been improved by splitting into four parallel phases. Consequently the delay of enhanced Carry- Save Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization.

A low-voltage and energy-efficient full adder cell based on carbon nanotube technology

Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET(Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP(Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.

Designing a Full Adder Circuit Based on Quasi-Floating Gate

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits

Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges recently.Undesirable leakage currents,the short-effect channel,and high energy dissipation are some of the concerns.Quantum-dot cellular automata(QCA)represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS.The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder.A low-complexity full adder block is beneficial for developing various intricate structures.This paper represents scalable 1-bit QCA full adder structures based on cell interaction.Our proposed full adders encompass preference aspects of QCA design,such as a low number of cells used,low latency,and small area occupation.Also,the proposed structures have been expanded to larger circuits,including a 4-bit ripple carry adder(RCA),a 4-bit ripple borrow subtractor(RBS),an add/sub circuit,and a 2-bit array multiplier.All designs were simulated and verified using QCA Designer-E version 2.2.This tool can estimate the energy dissipation as well as evaluate the performance of the circuits.Simulation results showed that the proposed designs are efficient in complexity,area,latency,cost,and energy dissipation.

An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending

We present a new counter-based Wallace-tree(CBW)8×8 multiplier.The multiplier’s counters are implemented with a new hybrid full adder(FA)cell,which is based on the transmission gate(TG)technique.The proposed FA,TG-based AND gate,and hybrid half adder(HA)generate M:3(4≤M≤7)digital counters with the ability to save at least 50%area occupation.Simulations by 90 nm technology prove the superiority of the proposed FA and digital counters under different conditions over the state-of-the-art designs.By using the proposed cells,the CBW multiplier exhibits high driving capability,low power consumption,and high speed.The CBW multiplier has a 0.0147 mm^(2)die area in a pad.The post-layout extraction proves the accuracy of experimental implementation.An image blending mechanism is proposed,in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW multiplier in image processing applications.The peak signal-to-noise ratio(PSNR)and structural similarity index metric(SSIM)are calculated as image quality parameters,and the results confirm that the presented CBW multiplier can be used as an alternative to designs in the literature.

Single-bit full adder and logic gate based on synthetic antiferromagnetic bilayer skyrmions

Skyrmion-based devices are promising candi-dates for non-volatile memory and low-delay time com-putation.Many skyrmion-based devices execute operation by controlling skyrmion trajectory,which can be impeded by the skyrmion Hall effect.Here,the design of skyrmion-based arithmetic devices built on synthetic antiferromag-netic(SyAF)structures is presented,where the structure can greatly suppress skyrmion Hall effect.In this study,the operations of skyrmion-based half adder,full adder,and XOR logic gate are executed by introducing geometric notches and tilted edges,which can annihilate or diverge skyrmion.Performance of these skyrmion-based devices is evaluated,where the delay time and energy-delay product of the single-bit full adder are 1.95 ns and 2.50×10^(-22)Js,which are only 12%and 79%those of the previously proposed skyrmion-based single-bit full adder.This improvement is significant in the construction of ripple-carry adder and ripple-carry adder-subtractor.Therefore,our skyrmion-based SyAF arithmetic device is a promising candidate to develop high-speed spintronic devices.

Design of a novel low power 8-transistor 1-bit full adder cell

An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors.An adder determines the overall performance of the circuits in most of those systems.In this paper we propose a novel 1-bit full adder cell which uses only eight transistors.In this design,three multiplexers and one inverter are applied tominimize the transistor count and reduce power consumption.The power dissipation,propagation delay,and power-delay produced using the new design are analyzed and com-pared with those of other designs using HSPICE simulations.The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value.The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.

基于量子元胞自动机的n位全加器设计

量子元胞自动机(Quantum-dot Cellular Automata,QCA)以其功耗低、纳米级设计、运算速度高等特点被认为是一门新兴技术,在不久的将来有望取代CMOS工艺,用于量子计算机的电路设计.近年来,在QCA电路中有很多使用三输入择多门(M3)和三输入异或门(XOR^(3))设计的全加器(Full Adder,FA).本文以这两种逻辑门为基础,结合QCA电路特有的时钟特点,设计了三种新型的n位全加器(FA1,FA2,FA3).FA1只使用了一个1位全加器,它的元胞的数量和电路面积比已发表的8位全加器至少减少了78%和90%,但一个时钟周期只能完成1位计算,延迟较大;FA2的元胞的数量和电路面积比已发表的8位全加器至少减少了47%和63%,可以在一个时钟周期内完成2位计算;FA3在一个时钟周期内可以进行4位计算,延迟最小.FA1、FA2和FA3作为n位全加器,随着全加器位数的增加,它们的元胞的数量和电路面积是不会改变的,这是以往设计所不能实现的.

基于EDA仿真软件Multisim在全加器设计中的应用探析

随着电子技术的快速发展,电子设计自动化(EDA)已经成为现代电子设计的重要手段。Multisim作为一种广泛应用于电子电路仿真与设计的软件,为相关领域的研究者、工程师提供了便捷的工具和平台。文章使用EDA仿真软件Multisim通过软件直接生成、利用软件作为辅助通过门电路、译码器、数据选择器设计实现全加器为例,探析Multisim在电子电路设计中的应用方法和优势。结果表明Multisim仿真软件设计电子电路在快速构建、仿真和优化全加器电路,以及提高设计效率和可靠性方面有明显优势。

高性能全加器电路版图优化设计研究

在现有全加器研究基础上,提出一种高性能全加器改进电路(improved full adder circuit,IFAC),通过改进全加器电路结构,优化电路元件工作数量,旨在提升加法器逻辑功能与运行状态。采用Candence软件搭载130 nm芯片锻造工艺,引入欧拉路径快速判寻法设计其电路版图,验证版图规则的合理性,并利用版图验证工具Dracula对电路进行仿真测试,结果表明本文所设计的全加器较常规全加器在处理复杂网络精确度、传输延迟时间、低功耗稳定运行及芯片面积方面有所提升。

超导单磁通量子数字电路的全加器设计与应用探索

随着超导单磁通量子(Single Flux Quantum,SFQ)数字电路的集成度规模不断提升,基于SFQ标准单元库及知识产权(Intellectual Property,IP)电路的设计将会逐渐取代原有的专用定制化数字电路设计的方式.与此同时,IP电路也可以作为新设计方法研究和新工艺及单元库可靠性的验证电路.本文选择大规模数字电路中的基础运算单元全加器为研究对象,希望能在尚在开发中的工艺下得到一个更加稳定工作和完整测试功能的全加器.本文基于自研SIMIT Nb03工艺上开发的SFQ单元库,设计了两种类型的全加器,且实现了全加器逻辑功能和工作性能的低频与高频测试表征.本文的第二种单级型全加器跟同类型的其他全加器相比,在保证了结数量和面积消耗偏小的优势下,又减少了设计难度和便于灵活扩展,使得其在电路IP化使用中也具有指导意义.低频测试结果表明,两种全加器均正确工作,其中单级型全加器具备良好的工作阈值.该款全加器的高频测试显示电路最高工作频率可达22 GHz.本文对测试结果进行详细分析,并基于此针对大规模电路实现开展简单应用探索.

基于压控自旋轨道矩磁性随机存储器的存内计算全加器设计

随着互补金属氧化物半导体技术的特征尺寸的不断缩小,其面临的静态功耗问题缩越来越突出。自旋磁随机存储器(MRAM)由于其非易失性、高速读写能力、高集成密度和CMOS兼容性等良好特性,受到了学术界的广泛关注和研究。该文采用电压调控的自旋轨道矩随机存储器设计了一个存内计算可重构逻辑阵列,能够实现全部布尔逻辑功能和高度并行计算。在此基础上设计了存内计算全加器并在40 nm工艺下进行了仿真验证。结果表明,与当前先进研究相比,该文提出的全加器具有更高的并行度,能够实现更快的计算速度(约1.11 ns/bit)和更低的计算功耗(约5.07 fJ/bit)。

自触发驱动的双极性脉冲叠加器

为了简化全固态双极性脉冲发生器中多个开关管的同步隔离驱动电路的复杂性,提出了一种自触发驱动的双极性脉冲叠加器。该电路将自触发驱动结构与特殊全桥电路相结合,只需提供2路隔离信号分别控制正、负极性第1级开关管,其他开关管通过自触发驱动电路逐级导通与关断,从而实现双极性高压脉冲输出。对电路的结构设计、工作原理、参数设计进行了分析,并利用Pspice软件对电路的可行性进行了仿真验证。所研制的15级电源样机上的实验结果表明:在10 k?阻性负载上产生了稳定的重频双极性脉冲,正压与负压幅值2~5 kV可调,脉宽1~10μs可调,频率0~1k Hz可调。该脉冲叠加器体积小巧,结构紧凑,可进行模块化设计,为研制小型化脉冲电源提供了技术支持。

45nm低功耗、高性能Zipper CMOS多米诺全加器设计

提出了电荷自补偿技术,此技术利用P型多米诺电路动态结点的放电对N型多米诺电路的动态结点充电,并在此技术基础上综合应用双阈值技术和多电源电压技术,设计了新型低功耗、高性能Zipper CMOS多米诺全加器.仿真过程中提出了功耗分布法,精确找到了电荷自补偿技术的最优路径.仿真结果表明,在相同的时间延迟下,与标准Zipper CMOS多米诺全加器、双阈值Zipper CMOS多米诺全加器、多电源电压Zipper CMOS多米诺全加器相比,新型Zipper CMOS多米诺全加器动态功耗分别减小了37%、35%和7%,静态功耗分别减小了41%,20%和43%.最后,分析并得到了新型全加器漏电流最低的输入矢量和时钟状态.