Global data traffic is growing rapidly,and the demand for optoelectronic transceivers applied in data centers(DCs)is also increasing correspondingly.In this review,we first briefly introduce the development of optoele...Global data traffic is growing rapidly,and the demand for optoelectronic transceivers applied in data centers(DCs)is also increasing correspondingly.In this review,we first briefly introduce the development of optoelectronics transceivers in DCs,as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process.We also summarize the research on the main components in silicon photonic transceivers.In particular,quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts.Some of the solutions for highspeed optical interconnection in DCs are then discussed.Among them,wavelength division multiplexing and four-level pulseamplitude modulation have been widely studied and applied.At present,the application of coherent optical communication technology has moved from the backbone network,to the metro network,and then to DCs.展开更多
The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main...The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve preci- sion of received data. The circuit simulation is based on Cadence’s spectre software and Taiwan Semiconduc- tor Manufacture Corporation’s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor (CMOS) model. The front and post-simulation results reveal that the transceiver designed can transmit and re- ceive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physi- cal-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.展开更多
Background The timing system of BEPC-Ⅱis established based on event generator and event receiver(EVR)modules from the Micro-Research Finland.Though it works smoothly,there are some downsides;for example,the output pu...Background The timing system of BEPC-Ⅱis established based on event generator and event receiver(EVR)modules from the Micro-Research Finland.Though it works smoothly,there are some downsides;for example,the output pulses cannot be adjusted in picosecond accuracy in EVRs,and additional hardware modules besides EVR had to be developed to generate the revolution frequency of synchrotron radiation ring of BEPC-Ⅱ.Purpose The purpose is to research the technique details of event timing system and to develop hardware modules by our-selves using FPGA,based on which further improvement in BEPC-Ⅱtiming system can be made.Results The homemade hardware cards have run successfully and generated synchronous trigger pulses and clocks.The jitter is under 15 ps.展开更多
基金supported by the National Key Research and Development Program of China under Grant No.2016YFB 0402302the National Natural Science Foundation of China under Grant No.91433206。
文摘Global data traffic is growing rapidly,and the demand for optoelectronic transceivers applied in data centers(DCs)is also increasing correspondingly.In this review,we first briefly introduce the development of optoelectronics transceivers in DCs,as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process.We also summarize the research on the main components in silicon photonic transceivers.In particular,quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts.Some of the solutions for highspeed optical interconnection in DCs are then discussed.Among them,wavelength division multiplexing and four-level pulseamplitude modulation have been widely studied and applied.At present,the application of coherent optical communication technology has moved from the backbone network,to the metro network,and then to DCs.
文摘The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve preci- sion of received data. The circuit simulation is based on Cadence’s spectre software and Taiwan Semiconduc- tor Manufacture Corporation’s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor (CMOS) model. The front and post-simulation results reveal that the transceiver designed can transmit and re- ceive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physi- cal-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.
文摘Background The timing system of BEPC-Ⅱis established based on event generator and event receiver(EVR)modules from the Micro-Research Finland.Though it works smoothly,there are some downsides;for example,the output pulses cannot be adjusted in picosecond accuracy in EVRs,and additional hardware modules besides EVR had to be developed to generate the revolution frequency of synchrotron radiation ring of BEPC-Ⅱ.Purpose The purpose is to research the technique details of event timing system and to develop hardware modules by our-selves using FPGA,based on which further improvement in BEPC-Ⅱtiming system can be made.Results The homemade hardware cards have run successfully and generated synchronous trigger pulses and clocks.The jitter is under 15 ps.
