The threshold voltage(V_(th))of the p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)is investigated via Silvaco-Atlas simulations.The main factors which influence the threshold voltage of p-channe...The threshold voltage(V_(th))of the p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)is investigated via Silvaco-Atlas simulations.The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier heightΦ_(1,p),polarization charge density σ_(b),and equivalent unite capacitance C_(oc).It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_(th),and threshold voltage|V_(th)|increases with the reduction in p-GaN doping concentration and the work-function of gate metal.Meanwhile,the increase in gate dielectric relative permittivity may cause the increase in threshold voltage|V_(th)|.Additionally,the parameter influencing output current most is the p-GaN doping concentration,and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10^(16) cm^(-3) at VGS=-12 V and VDS=-10 V.展开更多
Based on the self-terminating thermal oxidation-assisted wet etching technique,two kinds of enhancement mode Al_(2)O_(3)/GaN MOSFETs(metal-oxide-semiconductor field-effect transistors)separately with sapphire substrat...Based on the self-terminating thermal oxidation-assisted wet etching technique,two kinds of enhancement mode Al_(2)O_(3)/GaN MOSFETs(metal-oxide-semiconductor field-effect transistors)separately with sapphire substrate and Si sub-strate are prepared.It is found that the performance of sapphire substrate device is better than that of silicon substrate.Comparing these two devices,the maximum drain current of sapphire substrate device(401 mA/mm)is 1.76 times that of silicon substrate device(228 mA/mm),and the field-effect mobility(μ_(FEmax))of sapphire substrate device(176 cm^(2)/V·s)is 1.83 times that of silicon substrate device(96 cm^(2)/V·s).The conductive resistance of silicon substrate device is 21.2Ω-mm,while that of sapphire substrate device is only 15.2Ω·mm,which is 61%that of silicon substrate device.The significant difference in performance between sapphire substrate and Si substrate is related to the differences in interface and border trap near Al_(2)O_(3)/GaN interface.Experimental studies show that(i)interface/border trap density in the sapphire substrate device is one order of magnitude lower than in the Si substrate device,(ii)Both the border traps in Al_(2)O_(3) dielectric near Al_(2)O_(3)/GaN and the interface traps in Al_(2)O_(3)/GaN interface have a significantly effect on device channel mobility,and(iii)the properties of gallium nitride materials on different substrates are different due to wet etching.The research results in this work provide a reference for further optimizing the performances of silicon substrate devices.展开更多
Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications.Being still in an early development phase,vertical GaN devices are yet to be fully optimized and require car...Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications.Being still in an early development phase,vertical GaN devices are yet to be fully optimized and require careful studies to foster their development.In this work,we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs(TMOS’s)provided by TCAD simulations,enhancing the dependability of the adopted process optimization approaches.Specifically,two different TMOS devices are compared in terms of transfer-curve hysteresis(H)and subthreshold slope(SS),showing a≈75%H reduction along with a≈30%SS decrease.Simulations allow attributing the achieved improvements to a decrease in the border and interface traps,respectively.A sensitivity analysis is also carried out,allowing to quantify the additional trap density reduction required to minimize both figures of merit.展开更多
碳化硅金属氧化物半导体场效应管(Si C MOSFET)和氮化镓高电子迁移率晶体管(GaN HEMT)这两种器件内部存在容易捕获电子的"陷阱",会影响导电沟道的性能,进而影响器件的导通电阻。对SiC MOSFET和GaN HEMT各选取了一款典型的商...碳化硅金属氧化物半导体场效应管(Si C MOSFET)和氮化镓高电子迁移率晶体管(GaN HEMT)这两种器件内部存在容易捕获电子的"陷阱",会影响导电沟道的性能,进而影响器件的导通电阻。对SiC MOSFET和GaN HEMT各选取了一款典型的商用器件,分别对Si C MOSFET和GaN HEMT的导通电阻可靠性进行了测试。测试结果表明,Si C MOSFET的导通电阻变化量相对小,且应力停止后导通电阻可以恢复到初始状态,这说明其界面态陷阱密度比GaN HEMT更低,因此实际应用中无需考虑导通电阻的稳定性;而GaN HEMT的动态电阻变化较大,这极大地增加了导通损耗,影响系统的可靠性,因此在实际应用中需要考虑导通电阻变化对导通性能的影响。展开更多
基金Project supported by the Key-Area Research and Development Program of Guangdong Province,China(Grant Nos.2020B010174001 and 2020B010171002)the Ningbo Science and Technology Innovation Program 2025(Grant No.2019B10123)the National Natural Science Foundation of China(Grant No.62074122).
文摘The threshold voltage(V_(th))of the p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)is investigated via Silvaco-Atlas simulations.The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier heightΦ_(1,p),polarization charge density σ_(b),and equivalent unite capacitance C_(oc).It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_(th),and threshold voltage|V_(th)|increases with the reduction in p-GaN doping concentration and the work-function of gate metal.Meanwhile,the increase in gate dielectric relative permittivity may cause the increase in threshold voltage|V_(th)|.Additionally,the parameter influencing output current most is the p-GaN doping concentration,and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10^(16) cm^(-3) at VGS=-12 V and VDS=-10 V.
文摘为分析宽禁带半导体器件GaN MOSFET与Si MOSFET栅极驱动损耗、开关损耗的成因及关联参数,利用单相全桥逆变拓扑结构搭建功率开关器件应用测试平台,对GaN MOSFET和Si MOSFET在不同开关频率及器件工作温度下的效率进行测试比较。实验结果显示,开关频率为50 k Hz和120 k Hz时,基于增强型Ga N MOSFET的逆变器比基于Si MOSFET的效率分别高1.47%和1.6%;40℃,50℃,60℃,70℃温度对比实验时,基于增强型GaN MOSFET的逆变器效率比基于Si MOSFET的分别高1.8%,1.9%,2.0%和2.1%,表明开关频率递增或工作温度越高的工况下,增强型GaN MOSFET高效性能越明显。
基金Project supported by the Research on Key Techniques in Reliability of Low Power Sensor Chip for IOTIPS and the Technology Project of Headquarters,State Grid Corporation of China(Grant No.5700-202041397A-0-0-00).
文摘Based on the self-terminating thermal oxidation-assisted wet etching technique,two kinds of enhancement mode Al_(2)O_(3)/GaN MOSFETs(metal-oxide-semiconductor field-effect transistors)separately with sapphire substrate and Si sub-strate are prepared.It is found that the performance of sapphire substrate device is better than that of silicon substrate.Comparing these two devices,the maximum drain current of sapphire substrate device(401 mA/mm)is 1.76 times that of silicon substrate device(228 mA/mm),and the field-effect mobility(μ_(FEmax))of sapphire substrate device(176 cm^(2)/V·s)is 1.83 times that of silicon substrate device(96 cm^(2)/V·s).The conductive resistance of silicon substrate device is 21.2Ω-mm,while that of sapphire substrate device is only 15.2Ω·mm,which is 61%that of silicon substrate device.The significant difference in performance between sapphire substrate and Si substrate is related to the differences in interface and border trap near Al_(2)O_(3)/GaN interface.Experimental studies show that(i)interface/border trap density in the sapphire substrate device is one order of magnitude lower than in the Si substrate device,(ii)Both the border traps in Al_(2)O_(3) dielectric near Al_(2)O_(3)/GaN and the interface traps in Al_(2)O_(3)/GaN interface have a significantly effect on device channel mobility,and(iii)the properties of gallium nitride materials on different substrates are different due to wet etching.The research results in this work provide a reference for further optimizing the performances of silicon substrate devices.
基金funding from the Electronic Component Systems for European Leadership Joint Undertaking (ECSEL JU),under grant agreement No.101007229support from the European Union’s Horizon 2020 Research and Innovation Programme,Germany,France,Belgium,Austria,Sweden,Spain,and Italy
文摘Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications.Being still in an early development phase,vertical GaN devices are yet to be fully optimized and require careful studies to foster their development.In this work,we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs(TMOS’s)provided by TCAD simulations,enhancing the dependability of the adopted process optimization approaches.Specifically,two different TMOS devices are compared in terms of transfer-curve hysteresis(H)and subthreshold slope(SS),showing a≈75%H reduction along with a≈30%SS decrease.Simulations allow attributing the achieved improvements to a decrease in the border and interface traps,respectively.A sensitivity analysis is also carried out,allowing to quantify the additional trap density reduction required to minimize both figures of merit.
文摘碳化硅金属氧化物半导体场效应管(Si C MOSFET)和氮化镓高电子迁移率晶体管(GaN HEMT)这两种器件内部存在容易捕获电子的"陷阱",会影响导电沟道的性能,进而影响器件的导通电阻。对SiC MOSFET和GaN HEMT各选取了一款典型的商用器件,分别对Si C MOSFET和GaN HEMT的导通电阻可靠性进行了测试。测试结果表明,Si C MOSFET的导通电阻变化量相对小,且应力停止后导通电阻可以恢复到初始状态,这说明其界面态陷阱密度比GaN HEMT更低,因此实际应用中无需考虑导通电阻的稳定性;而GaN HEMT的动态电阻变化较大,这极大地增加了导通损耗,影响系统的可靠性,因此在实际应用中需要考虑导通电阻变化对导通性能的影响。
