A 59mW 10b 40Msample/s Pipelined ADC

This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is realized using just four amplifiers with a separate sample-and-hold block. It employs two key techniques： a high bandwidth low-power gain-boosting telescopic amplifiers technique and a low power low offset dynamic comparators technique.The ADC achieves a 8.1 effective number of bits,a maximum differential nonlinearity of a 0.85 least significant bit（LSB）, and maximum integral nonlinearity of 2.2LSB for a 0.5MHz input at full sampling rate. It occupies 1.24mm^2 ,which also includes a bandgap and a voltage reference circuit and dissipates only 59mW.

A High Linearity,13bit Pipelined CMOS ADC

A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.

A 1.8V 10bit 100Msps Pipelined Analog to Digital Converter

A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch ＂on＂ resistance. With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter （ADC） achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit （S/H） and the sub-stages. Based on these methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltage supply. The ADC achieves an SNR of 54. 2dB （input frequency of 6.26MHz） and an SNR of 49. 8dB （input frequency of 48. 96MHz） when the sampling frequency is 100MHz.

Design and Analysis of a Gain-Enhanced,Fully Differential Telescopic Operational Transconductance Amplifier

This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications of the OTA are derived from the requirements of ADC. Simulation shows that for a lpF load capacitance, this OTA achieves a high DC gain （approximately 145dB） and a wide unity-gain bandwidth （above 750MHz） at a phase margin 58°. In a configuration where the closed loop-gain is 4,the design spends about 18ns for settling with 0.05% accuracy. Simulations of this design are performed in SMIC CMOS 0.18μm technology.

A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.

A sample and hold circuit for pipelined ADC

A high performance sample-and-hold(S/H) circuit used in a pipelined analog-to-digital converter(ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit.A gain-boosted folded cascode operational transconductance amplifier(OTA) with a DC gain of 90 dB and a GBW of 738 MHz was designed. A low supply voltage bootstrapped switch was used to improve the linearity of the S/H circuit. With these techniques, the designed S/H circuit can reach 94 dB SFDR for a 48.9 MHz input frequency with 100 MS/s sampling rate. Measurement results of a 14-bit 100-MS/s pipeline ADC with designed S/H circuit are presented.