A DESIGN METHODOLOGY FOR LOW-LEAKAGE AND HIGHPERFORMANCE BUFFER BASED ON DEVIANT BEHAVIOR OF GATE LEAKAGE

Based on the observation that both subthreshold and gate leakage depend on transistors width, this paper introduces a feasible method to fast estimate leakage current in buffers. In simulating of leakage current with swept transistor width, we found that gate leakage is not always a linear function of the device geometry. Subsequently, this paper presented the theoretical analysis and experimental evidence of this exceptional gate leakage behavior and developed a design methodology to devise a low-leakage and high-performance buffer with no penalty in area using this deviation.

Modified model of gate leakage currents in AlGaN/GaN HEMTs

It has been reported that the gate leakage currents are described by the Frenkel-Poole emission(FPE) model,at temperatures higher than 250 K.However,the gate leakage currents of our passivated devices do not accord with the FPE model.Therefore,a modified FPE model is developed in which an additional leakage current,besides the gate(ⅠⅡ),is added.Based on the samples with different passivations,the ⅠⅡcaused by a large number of surface traps is separated from total gate currents,and is found to be linear with respect to(φB-Vg)0.5.Compared with these from the FPE model,the calculated results from the modified model agree well with the Ig-Vgmeasurements at temperatures ranging from 295 K to 475 K.

Effect of SiN:H_x passivation layer on the reverse gate leakage current in GaN HEMTs

This paper concentrates on the impact of SiN passivation layer deposited by plasma-enhanced chemical vapor deposition（PECVD） on the Schottky characteristics in GaN high electron mobility transistors（HEMTs）. Three types of SiN layers with different deposition conditions were deposited on GaN HEMTs. Atomic force microscope（AFM）, capacitance-voltage（C-V）, and Fourier transform infrared（FTIR） measurement were used to analyze the surface morphology, the electrical characterization, and the chemical bonding of SiN thin films, respectively. The better surface morphology was achieved from the device with lower gate leakage current. The fixed positive charge Qf was extracted from C-V curves of Al/SiN/Si structures and quite different density of trap states（in the order of magnitude of 1011-1012 cm^（-2）） was observed.It was found that the least trap states were in accordance with the lowest gate leakage current. Furthermore, the chemical bonds and the %H in Si-H and N-H were figured from FTIR measurement, demonstrating an increase in the density of Qf with the increasing %H in N-H. It reveals that the effect of SiN passivation can be improved in GaN-based HEMTs by modulating %H in Si-H and N-H, thus achieving a better Schottky characteristics.

The passivation mechanism of nitrogen ions on the gate leakage current of HfO_2/AlGaN/GaN MOS-HEMTs

In this paper, we systematically study the positive gate leakage current in AlGaN/GaN metal-oxide-semiconductor high electron-mobility transistors (MOS-HEMTs) with HfO 2 dielectric using atomic layer deposition (ALD). We observe that the incorporated nitrogen ions will improve the positive gate leakage current of devices obviously, but do not change the reverse gate leakage current. The passivation mechanism of nitrogen ions in oxygen vacancies in HfO 2 is studied by first-principles calculations. It is shown that the gap states of HfO 2 caused by oxygen vacancies increase the positive gate leakage current of MOS-HEMTs. Nitrogen ions passivate the gap states of HfO 2 and decrease the positive gate leakage current but do not effect the reverse gate leakage current.

Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications

We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.

Enhancement-mode InAlN/GaN MISHEMT with low gate leakage current

We report an enhancement-mode InAlN/GaN MISHEMT with a low gate leakage current by a thermal oxidation technique under gate.The off-state source-drain current density is as low as～10^（17） A/mm at V_（GS）= 0 V and V_（DS） = 5 V.The threshold voltage is measured to be ＋0.8 V by linear extrapolation from the transfer characteristics.The E-mode device exhibits a peak transconductance of 179 mS/mm at a gate bias of 3.4 V.A low reverse gate leakage current density of 4.9×10^（17） A/mm is measured at V_（GS） =-15 V.

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al_2O_3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.

Effect of the post-gate annealing on the gate reliability of AlGaN/GaN HEMTs

In this paper,we investigated the effect of post-gate annealing(PGA)on reverse gate leakage and the reverse bias reliability of Al_(0.23)Ga_(0.77)N/GaN high electron mobility transistors(HEMTs).We found that the Poole-Frenkel(PF)emission is dominant in the reverse gate leakage current at the low reverse bias region(V_(th)<V_(G)<0 V)for the unannealed and annealed HEMTs.The emission barrier height of HEMT is increased from 0.139 to 0.256 eV after the PGA process,which results in a reduction of the reverse leakage current by more than one order.Besides,the reverse step stress was conducted to study the gate reliability of both HEMTs.After the stress,the unannealed HEMT shows a higher reverse leakage current due to the permanent damage of the Schottky gate.In contrast,the annealed HEMT shows a little change in reverse leakage current.This indicates that the PGA can reduce the reverse gate leakage and improve the gate reliability.

Improved device performance of recessed-gate AlGaN/GaN HEMTs by using in-situ N_(2)O radical treatment

The N_(2)O radicals in-situ treatment on gate region has been employed to improve device performance of recessedgate Al Ga N/Ga N high-electron-mobility transistors(HEMTs).The samples after gate recess etching were treated by N_(2)O radicals without physical bombardment.After in-situ treatment(IST)processing,the gate leakage currents decreased by more than one order of magnitude compared to the sample without IST.The fabricated HEMTs with the IST process show a low reverse gate current of 10;A/mm,high on/off current ratio of 108,and high f_(T)×L_(g)of 13.44 GHz·μm.A transmission electron microscope(TEM)imaging illustrates an oxide layer with a thickness of 1.8 nm exists at the AlGaN surface.X-ray photoelectron spectroscopy(XPS)measurement shows that the content of the Al-O and Ga-O bonds elevated after IST,indicating that the Al-N and Ga-N bonds on the AlGaN surface were broken and meanwhile the Al-O and Ga-O bonds formed.The oxide formed by a chemical reaction between radicals and the surface of the AlGaN barrier layer is responsible for improved device characteristics.

The leakage current mechanisms in the Schottky diode with a thin Al layer insertion between Al_(0.245)Ga_(0.755)N/GaN heterostructure and Ni/Au Schottky contact

This paper investigates the behaviour of the reverse-bias leakage current of the Schottky diode with a thin Al inserting layer inserted between Al0.245Ga0.755N/GaN heterostructure and Ni/Au Schottky contact in the temperature range of 25 350℃. It compares with the Schottky diode without Aluminium inserting layer. The experimental results show that in the Schottky diode with Al layer the minimum point of I-V curve drifts to the minus voltage, and with the increase of temperature increasing, the minimum point of I V curve returns the 0 point. The temperature dependence of gate-leakage currents in the novelty diode and the traditional diode are studied. The results show that the Al inserting layer introduces interface states between metal and Al0.245Ga0.755N. Aluminium reacted with oxygen formed Al2O3 insulator layer which suppresses the trap tunnelling current and the trend of thermionic field emission current. The reliability of the diode at the high temperature is improved by inserting a thin Al layer.

Leakage Analysis of a Low Power 10 Transistor SRAM Cell in 90 nm Technology

In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employed in the 10 Transistor SRAM cell to reduce active power consumption during the write operation. Read access time and write access time are measured for proposed cell architecture based on Eldo SPICE simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology at various process corners. Leakage current measurements made on hold mode of operation show that proposed cell architecture is having 12.31 nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor cell. 10 Transistor cell also has better performance in terms of leakage power as compared to 6 Transistor cell.

Performance analysis of GaN-based high-electron-mobility transistors with postpassivation plasma treatment

AlGaN/GaN high-electron-mobility transistors(HEMTs)with postpassivation plasma treatment are demonstrated and investigated for the first time.The results show that postpassivation plasma treatment can reduce the gate leakage and enhance the drain current.Comparing with the conventional devices,the gate leakage of Al Ga N/Ga N HEMTs with postpassivation plasma decreases greatly while the drain current increases.Capacitance-voltage measurement and frequencydependent conductance method are used to study the surface and interface traps.The mechanism analysis indicates that the surface traps in the access region can be reduced by postpassivation plasma treatment and thus suppress the effect of virtual gate,which can explain the improvement of DC characteristics of devices.Moreover,the density and time constant of interface traps under the gate are extracted and analyzed.

Performance comparison of Pt/Au and Ni/Au Schottky contacts on Al_xGa_(1-x)N/GaN heterostructures at high temperatures

In contrast with Au/Ni/Al0.25Ga0.75N/GaN Schottky contacts, this paper systematically investigates the effect of thermal annealing of Au/Pt/Alo.25Ga0.75N/GaN structures on electrical properties of the two-dimensional electron gas in Alo.25Ga0.75N/CaN heterostructures by means of temperature-dependent Hall and temperature-dependent current-voltage measurements. The two-dimensional electron gas density of the samples with Pt cap layer increases after annealing in N2 ambience at 600℃ while the annealing treatment has little effect on the two-dimensional electron gas mobility in comparison with the samples with Ni cap layer. The experimental results indicate that the Au/Pt/Al0.25Ga0.75N/GaN Schottky contacts reduce the reverse leakage current density at high annealing temperatures of 400-600 ℃. As a conclusion, the better thermal stability of the Au/Pt/Alo.25Gao.75N/GaN Schottky contacts than the Au/Ni/Al0.25Ga0.75N/GaN Schottky contacts at high temperatures can be attributed to the inertness of the interface between Pt and AlxGa1-xN.

Post-Gate Process Annealing Effects of Recessed AlGaN/GaN HEMTs

This paper focuses on how to reduce the gate leakage current caused by plasma dry etching. X-ray photoelectron spectroscopy （XPS） is employed to measure the AlGaN surface before and after etching. N vacancies are introduced, which cause that gate currents are not dominated by the thermal electron emission mechanism. N vacancies enhance the tunneling effect and reduce the Schottky barrier height as n-type doped in the etched AIGaN surface.A post-gate process for AlGaN/GaN HEMTs,annealing at 400℃ in a nitrogen ambient for 10min is introduced. After annealing, Ni atoms of gate metal reacted with Ga atoms of AlGaN, and N vacancies were reduced. The reverse leakage decreased by three orders of magnitude,the forward turn-on voltage increased and the ideality factor reduced from 3.07 to 2.08.

Effective interface passivation of a Ge/HfO_2 gate stack using ozone pre-gate treatment and ozone ambient annealing

The physical and electrical properties of a Ge/GeO2/HfO2/Al gate stack are investigated.A thin interfacial GeO2 layer（- 1 nm） is formed between Ge and HfO2 by dual ozone treatments,which passivates the Ge/high-k interface.Capacitors on p-type Ge substrates show very promising capacitance-voltage（C-V） characteristics by using in situ pre-gate ozone passivation and ozone ambient annealing after high-k deposition,indicating efficient passivation of the Ge/HfO2 interface.It is shown that the mid-gap interface state density at the Ge/GeO2 interface is 6.4×10^11 cm^-2·eV^-1.In addition,the gate leakage current density of the Ge/GeO2/HfO2/Al gate stack passivated by the dual ozone treatments is reduced by about three orders of magnitude compared to that of a Ge/HfO2/Al gate stack without interface passivation.

Preparation of a new gate dielectric material HfTiON film

A new gate dielectric material HfTiON is deposited by reactive co-sputtering of Hf and Ti targets in N2/O2 ambient, followed by annealing in N2 at 600 ℃ and 800 ℃ respectively for 2 min. Capacitance-voltage and gate-leakage properties are characterized and compared for different anneal conditions. The results indicate that the sample annealed at 800 ℃ exhibits lower interface-state and oxide-charge densities, and better device reliability. This is attributed to the fact that the rapid thermal annealing at the higher temperature of 800 ℃ can effectively remove the damage-induced precipitation, forming a hardened dielectric/Si interface with high reliability.

Annealing before gate metal deposition related noise performance in AlGaN/GaN HEMTs

For a further improvement of the noise performance in A1GaN/GaN HEMTs, reducing the relatively high gate leakage current is a key issue. In this paper, an experiment was carried out to demonstrate that one method during the device fabrication process can lower the noise. Two samples were treated differently after gate recess etching： one sample was annealed before metal deposition and the other sample was left as it is. From a comparison of their Ig-Vg characteristics, a conclusion could be drawn that the annealing can effectively reduce the gate leakage current. The etching plasma-induced damage removal or reduction after annealing is considered to be the main factor responsible for it. Evidence is given to prove that annealing can increase the Schottky barrier height. A noise model was used to verify that the annealing of the gate recess before the metal deposition is really effective to improve the noise performance of AIGaN/GaN HEMTs.

A gate current 1/f noise model for GaN/AlGaN HEMTs

This work presents a theoretical and experimental study on the gate current 1/f noise in Al GaN/GaN HEMTs. Based on the carrier number fluctuation in the two-dimensional electron gas channel of Al GaN/GaN HEMTs, a gate current 1/f noise model containing a trap-assisted tunneling current and a space charge limited current is built. The simulation results are in good agreement with the experiment. Experiments show that, if Vg〈Vx（critical gate voltage of dielectric relaxation）, gate current 1/f noise comes from the superimposition of trapassisted tunneling RTS（random telegraph noise）, while Vg 〉Vx, gate current 1/f noise comes from not only the trap-assisted tunneling RTS, but also the space charge limited current RTS. This indicates that the gate current 1/f noise of the GaN-based HEMTs device is sensitive to the interaction of defects and the piezoelectric relaxation. It provides a useful characterization tool for deeper information about the defects and their evolution in Al GaN/GaN HEMTs.