A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input sta...A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm^2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.展开更多
A double silicon on insulator（DSOI） structure was introduced based on fully depleted SOI（FDSOI）technology.The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to ...A double silicon on insulator（DSOI） structure was introduced based on fully depleted SOI（FDSOI）technology.The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to N-channel and P-channel devices.Based on DSOI ring oscillator（OSC）,this paper focused on the theoretical analysis and electrical test of how the OSC＇s frequency being influenced by the back gate electrodes（soi2n,soi2p）.The testing results showed that the frequency and power consumption of OSC could change nearly linearly along with the back gate bias.According to the different requirements of the circuit designers,the circuit performance could be improved by positive soi2 n and negative soi2 p,and the power consumption could be reduced by negative soi2n and positive soi2p.The best compromise between performance and power consumption of the circuit could be achieved by appropriate back gate biasing.展开更多
基金supported by the Important National Science and Technology Specific Projects of China(No.2009ZX01031-003-002)
文摘A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm^2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.
文摘A double silicon on insulator（DSOI） structure was introduced based on fully depleted SOI（FDSOI）technology.The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to N-channel and P-channel devices.Based on DSOI ring oscillator（OSC）,this paper focused on the theoretical analysis and electrical test of how the OSC＇s frequency being influenced by the back gate electrodes（soi2n,soi2p）.The testing results showed that the frequency and power consumption of OSC could change nearly linearly along with the back gate bias.According to the different requirements of the circuit designers,the circuit performance could be improved by positive soi2 n and negative soi2 p,and the power consumption could be reduced by negative soi2n and positive soi2p.The best compromise between performance and power consumption of the circuit could be achieved by appropriate back gate biasing.
