A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation

A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.

BER ANALYSIS OF A GMSK SYSTEM USING DECISION FEEDBACK

There are considerable literatures on the Bit Error Rate(BER)evaluation of DifferentialDetection of Gaussian Minimum Shift Keying(DDGMSK)system using Decision Feedback(DF),butmost of them give the performance based on the Monte Carlo Error Counting(MCEC)technique.Fromthe probability distribution of the phase angle between two vectors perturbed by Gaussian noises,theformulae of BER are derived for the performance analysis of DDGMSK system with DF in this letter.Considering the m-bit dock-tailed sequence,the new formulae of Gaussian Minimum Shift Keying(GMSK)modulated phase and the Time-Varying Signal to Noise Ratio(TVSNR)of the demodulatedsignal are presented,and it is proved that the relationship between the TVSNR of the demodulatedsignal and the size of eye opening is not inevitable.Simulation results show that the theoretical in-vestigation gives analogous results with the MCEC technique.The formulae presented are useful for theperformance analysis of systems using GMSK as modulating and demodulating method,for instance,the analysis of synchronous performance of frequency-hopping communication system.