Types of hybrid architectures survivor memory unit (SMU) is presented,which are applicable to IEEE 802.3 ab 1000 Base-T Gigabit Ethernet (GbE) transceiver. Area, power and decoder latency were taken into account and m...Types of hybrid architectures survivor memory unit (SMU) is presented,which are applicable to IEEE 802.3 ab 1000 Base-T Gigabit Ethernet (GbE) transceiver. Area, power and decoder latency were taken into account and most efficient architectures were compared to optimize area/power tradeoff in different kinds of applications. Suitable SMU architectures are given out respectively in area-restrict, power-restrict and latency-restrict designs. A power-efficient architecture was selected in our GbE project. It provides 48% improvement in area and 71% amelioration in power, compared to classical register exchange architecture (REA) SMU.展开更多
Systems containing multiple graphics-processing-unit(GPU)clusters are difficult to use for real-time electroholography when using only a single spatial light modulator because the transfer of the computer-generated ho...Systems containing multiple graphics-processing-unit(GPU)clusters are difficult to use for real-time electroholography when using only a single spatial light modulator because the transfer of the computer-generated hologram data between the GPUs is bottlenecked.To overcome this bottleneck,we propose a rapid GPU packing scheme that significantly reduces the volume of the required data transfer.The proposed method uses a multi-GPU cluster system connected with a cost-effective gigabit Ethernet network.In tests,we achieved real-time electroholography of a three-dimensional(3D)video presenting a point-cloud 3D object made up of approximately 200,000 points.展开更多
A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input pa...A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.展开更多
In this paper, a novel reconfiguration technique is developed in the context of a fault-tolerant Networked Control System (NCS) in two train wagons. All sensors, controllers and actuators in both wagons are connected ...In this paper, a novel reconfiguration technique is developed in the context of a fault-tolerant Networked Control System (NCS) in two train wagons. All sensors, controllers and actuators in both wagons are connected on top of a single Gigabit Ethernet network. The network also carries wired and wireless entertainment loads. A Markov model is used to prove that this reconfiguration technique reduces the effect of a failure in the error detection and switching mechanisms on the reliability of the control function. All calculations are based on closed-form solutions and verified using the SHARPE software package.展开更多
ZYNQ-Ultrascale+型器件是Xilinx公司推出的MPSoC(Multi-Processor System on Chip)架构器件,上面集成了多核Cortex-A53处理器以及Ultrscale系列的FPGA(Field-Programmable Gate Array)。对如今越来越复杂的网络环境以及越来越庞大的网...ZYNQ-Ultrascale+型器件是Xilinx公司推出的MPSoC(Multi-Processor System on Chip)架构器件,上面集成了多核Cortex-A53处理器以及Ultrscale系列的FPGA(Field-Programmable Gate Array)。对如今越来越复杂的网络环境以及越来越庞大的网络数据吞吐的管理问题进行了研究,采用了ZYNQ-Ultrascale+型器件作为核心处理器,提出了一种万兆以太网流信息统计架构。通过对以太网链路的数据包进行卸载,组合成流信息进行统计分析,将统计结果传输至主机,能够完成对万兆以太网的管理。将所述的架构应用于实际的万兆以太网监控系统中,支持TCP、UDP、ICMP、ARP等协议的统计,统计延时小于5μs,最高可支持3.2k条流数量。展开更多
基金National Science Fund for Creative ResearchGroups (No.60521002)Shanghai NaturalScience Foundation(No.037062022)
文摘Types of hybrid architectures survivor memory unit (SMU) is presented,which are applicable to IEEE 802.3 ab 1000 Base-T Gigabit Ethernet (GbE) transceiver. Area, power and decoder latency were taken into account and most efficient architectures were compared to optimize area/power tradeoff in different kinds of applications. Suitable SMU architectures are given out respectively in area-restrict, power-restrict and latency-restrict designs. A power-efficient architecture was selected in our GbE project. It provides 48% improvement in area and 71% amelioration in power, compared to classical register exchange architecture (REA) SMU.
基金supported by the Japan Society for the Promotion of Science(JSPS)KAKENHI(Nos.18K11399 and 19H01097)the Telecommunications Advancement Foundation.
文摘Systems containing multiple graphics-processing-unit(GPU)clusters are difficult to use for real-time electroholography when using only a single spatial light modulator because the transfer of the computer-generated hologram data between the GPUs is bottlenecked.To overcome this bottleneck,we propose a rapid GPU packing scheme that significantly reduces the volume of the required data transfer.The proposed method uses a multi-GPU cluster system connected with a cost-effective gigabit Ethernet network.In tests,we achieved real-time electroholography of a three-dimensional(3D)video presenting a point-cloud 3D object made up of approximately 200,000 points.
基金supported by the National Natural Science Foundation of China(Nos.60536030,60502005)the National High Technology Research and Development Program of China(Nos.2007AA01Z2A5,2006AA01Z239,2007AA03Z454)
文摘A zero-pole cancellation transimpedance amplifier（TIA）has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply.
文摘In this paper, a novel reconfiguration technique is developed in the context of a fault-tolerant Networked Control System (NCS) in two train wagons. All sensors, controllers and actuators in both wagons are connected on top of a single Gigabit Ethernet network. The network also carries wired and wireless entertainment loads. A Markov model is used to prove that this reconfiguration technique reduces the effect of a failure in the error detection and switching mechanisms on the reliability of the control function. All calculations are based on closed-form solutions and verified using the SHARPE software package.
文摘ZYNQ-Ultrascale+型器件是Xilinx公司推出的MPSoC(Multi-Processor System on Chip)架构器件,上面集成了多核Cortex-A53处理器以及Ultrscale系列的FPGA(Field-Programmable Gate Array)。对如今越来越复杂的网络环境以及越来越庞大的网络数据吞吐的管理问题进行了研究,采用了ZYNQ-Ultrascale+型器件作为核心处理器,提出了一种万兆以太网流信息统计架构。通过对以太网链路的数据包进行卸载,组合成流信息进行统计分析,将统计结果传输至主机,能够完成对万兆以太网的管理。将所述的架构应用于实际的万兆以太网监控系统中,支持TCP、UDP、ICMP、ARP等协议的统计,统计延时小于5μs,最高可支持3.2k条流数量。
