Gray code based gradient-free optimization algorithm for parameterized quantum circuit

A Gray code based gradient-free optimization(GCO)algorithm is proposed to update the parameters of parameterized quantum circuits(PQCs)in this work.Each parameter of PQCs is encoded as a binary string,named as a gene,and a genetic-based method is adopted to select the offsprings.The individuals in the offspring are decoded in Gray code way to keep Hamming distance,and then are evaluated to obtain the best one with the lowest cost value in each iteration.The algorithm is performed iteratively for all parameters one by one until the cost value satisfies the stop condition or the number of iterations is reached.The GCO algorithm is demonstrated for classification tasks in Iris and MNIST datasets,and their performance are compared by those with the Bayesian optimization algorithm and binary code based optimization algorithm.The simulation results show that the GCO algorithm can reach high accuracies steadily for quantum classification tasks.Importantly,the GCO algorithm has a robust performance in the noise environment.

Low complexity DCT-based distributed source coding with Gray code for hyperspectral images

To compress hyperspectral images, a low complexity discrete cosine transform （DCT）-based distributed source coding （DSC） scheme with Gray code is proposed. Unlike most of the existing DSC schemes, which utilize transform in spatial domain, the proposed algorithm applies transform in spectral domain. Set-partitioning-based approach is applied to reorganize DCT coefficients into waveletlike tree structure and extract the sign, refinement, and significance bitplanes. The extracted refinement bits are Gray encoded. Because of the dependency along the line dimension of hyperspectral images, low density paritycheck-（LDPC）-based Slepian-Wolf coder is adopted to implement the DSC strategy. Experimental results on airborne visible/infrared imaging spectrometer （AVIRIS） dataset show that the proposed paradigm achieves up to 6 dB improvement over DSC-based coders which apply transform in spatial domain, with significantly reduced computational complexity and memory storage.

Absolute multi-pole encoder with a simple structure based on an improved gray code to enhance the resolution

We developed a novel absolute multi-pole encoder structure to improve the resolution of the multi-pole encoder, realize absolute output and reduce the manufacturing cost of the encoder. The structure includes two ring alnicos defined as index track and sub-division track, respectively. The index track is magnetized based on the improved gray code, with linear halls placed around the track evenly. The outputs of linear halls show the region the rotor belongs to. The sub-division track is magnetized to N-S-N-S (north-south-north-south), and the number of N-S pole pairs is determined by the index track. Three linear hall sensors with an air-gap of 2 mm are used to translate the magnetic filed to voltage signals. The relative offset in a single N-S is obtained through look-up. The magnetic encoder is calibrated using a higher-resolution incremental optical encoder. The pulse output from the optical encoder and hall signals from the magnetic encoder are sampled at the same time and transmitted to a computer, and the relation between them is calculated, and stored in the FLASH of MCU (micro controller unit) for look-up. In the working state, the absolute angle is derived by looking-up with hall signals. The structure is simple and the manufacturing cost is very low and suitable for mass production.

Area Query Processing Based on Gray Code in Wireless Sensor Networks

Area query processing is significant for various applications of wireless sensor networks since it can request information of particular areas in the monitored environment. Existing query processing techniques cannot solve area queries. Intuitively, centralized processing on Base Station can accomplish area queries via collecting information from all sensor nodes. However, this method is not suitable for wireless sensor networks with limited energy since a large amount of energy is wasted for reporting useless data. This motivates us to propose an energy-efficient in-network area query processing scheme. In our scheme, the monitored area is partitioned into grids, and a unique gray code number is used to represent a Grid ID （GID）, which is also an effective way to describe an area. Furthermore, a reporting tree is constructed to process area merging and data aggregations. Based on the properties of GIDs, subareas can be merged easily and useless data can be discarded as early as possible to reduce energy consumption. For energy-efficiently answering continuous queries, we also design an incremental update method to continuously generate query results. In essence, all of these strategies are pivots to conserve energy consumption. With a thorough simulation study, it is shown that our scheme is effective and energy-efficient

A RIGOROUS PROOF ON CIRCULAR WIRELENGTH FOR HYPERCUBES

We study embeddings of the n-dimensional hypercube into the circuit with 2nvertices.We prove that the circular wirelength attains a minimum by gray coding;that was called the CT conjecture by Chavez and Trapp(Discrete Applied Mathematics,1998).This problem had claimed to be settled by Ching-Jung Guu in her doctoral dissertation“The circular wirelength problem for hypercubes”(University of California,Riverside,1997).Many argue there are gaps in her proof.We eliminate the gaps in her dissertation.

CHAOTIC TRANSDUCER

Utilizing the character of chaos, the sensitivity to the initial conditions, the concept and the structure of so-called chaotic transducer based on Tent map is provided in this paper creatively. The possibility of applying the basic theory of symbolic dynamics to the measurement is presented and proved. Then, the theoretical model of chaotic transducer is realized by using the switched capacitor and the basic experimental results are given. The transducer has such characters as high sensitivity, resolution, the simple structure and combining signal amplification with A/D. The new area of the application of chaos is exploited. Meanwhile, it provides a new method of exploring the structure of new type transducer.

机铰式注塑机锁模力的精确检测、自动调整及修正

注塑机更换模具后,由于模具厚度的改变,需要对机器进行匹配性调整,从而获得合适的锁模位置及锁模力。传统的机铰式注塑机往往采用渐近式的多次调整来达到近似的锁模力,但存在自动调模周期过长、成功率偏低的缺点。该文描述的方案将采用拉杆拉伸检测传感器,对锁模力进行精确地检测,并通过控制软件程序,实现锁模力快速、自动调整和修正的功能。

3D surface reconstruction based on binocular vision using structured light

A 3D surface reconstruction method using a binocular stereo vision technology and a coded structured light,which combines a gray code with phase-shift has been studied.The accuracy of the 3 D surface reconstruction mainly depends on the decoding of gray code views and phase-shift views.In order to find the boundary accurately,gray code patterns and their inverses are projected onto a human eye plaster model.The period dislocation between the gray code views and the phase-shift views in the course of decoding has been analyzed and a new method has been proposed to solve it.The splicing method is based on feature points.The result of the 3D surface reconstruction shows the accuracy and reliability of our method.

FPGA-Based High-Frequency Digital Pulse Width Modulator Architecture for DC-DC Converters

Digital pulse width modulator is an integral part in digitally controlled Direct Current to Direct Current (DC-DC) converter utilized in modern portable devices. This paper presents a new Digital Pulse Width Modulator (DPWM) architecture for DC-DC converter using mealy finite state machine with gray code encoding scheme and one hot encoding method to derive the variable duty cycle Pulse Width Modulation (PWM) signal without varying the clock frequency. To verify the proposed DPWM technique, the architecture with control input of six, five and four bits are implemented and the maximum operating frequency along with power consumption results is obtained for different Field Programmable Gate Array (FPGA) devices. The post layout timing results are presented showing that architecture can work with maximum frequency of 326 MHz and derive PWM signal of 3.59 MHz. Experimental results show the implementation of the proposed architecture in low-cost FPGA (Spartan 3A) with on-board oscillator clock frequency of 12 MHz which is multiplied internally by two with Digital Clock Manager (DCM) and derive the PWM signal of 1.5 MHz with a time resolution of 1 ps.

A 14-bit wide temperature range differential SAR ADC with an on-chip multi-segment BGR

A 14-bit low power self-timed differential successive approximation（SAR） ADC with an on-chip multisegment bandgap reference（BGR） is described.An on-chip multi-segment BGR,which has a temperature coefficient of 1.3 ppm/℃and a thermal drift of about 100μV over the temperature range of -40 to 120℃is implemented to provide a high precision reference voltage for the SAR ADC.The Gray code form is utilized instead of binary form mode control to reduce substrate noise and enhance the linearity of the whole system.Self-timed bit-cycling is adopted to enhance the time efficiency.The 14-bit ADC was fabricated in a TSMC 0.13μm CMOS process. With the on-chip BGR,the SAR ADC achieves an SNDR of 81.2 dB（13.2 ENOB） and an SFDR of 85.2 dB with a conversion rate of 2 MS/s at room temperature and can keep an ENOB of more than 12 bits at a conversion rate of 2 MS/s over the temperature range from -40 to 120℃.

Generating Combinations by Three Basic Operations

We investigate the problem of listing combinations using a special class of operations, prefix shifts. Combinations are represented as bitstrings of O＇s and l＇s, and prefix shifts are the operations of rotating some prefix of a bitstring by one position to left or right. We give a negative answer to an open problem asked by F. Ruskey and A. Williams （Generating combinations by prefix shifts, In Proc. llth Annual International Computing and Combinatorics Conference 2005, LNCS 3595, Springer, 2005, pp.570-576）, that is whether we can generate combinations by only using three very basic prefix shifts on bitstrings, which are transposition of the first two bits and the rotation of the entire bitstring by one position in either direction （i.e., applying the permutations σ2, σn and σn^-1 to the indices of the bitstrings）.