Multiprocessor System on Chip (MPSoC) technology presents an interesting solution to reduce the computational time of complex applications such as multimedia applications. Implementing the new High Efficiency Video Co...Multiprocessor System on Chip (MPSoC) technology presents an interesting solution to reduce the computational time of complex applications such as multimedia applications. Implementing the new High Efficiency Video Coding (HEVC/h.265) codec on the MPSoC architecture becomes an interesting research point that can reduce its algorithmic complexity and resolve the real time constraints. The implementation consists of a set of steps that compose the Co-design flow of an embedded system design process. One of the first anf key steps of a Co-design flow is the modeling phase which allows designers to make best architectural choices in order to meet user requirements and platform constraints. Multimedia applications such as HEVC decoder are complex applications that demand increasing degrees of agility and flexibility. These applications are usually modeling by dataflow techniques. Several extensions with several schedules techniques of dataflow model of computation have been proposed to support dynamic behavior changes while preserving static analyzability. In this paper, the HEVC/h.265 video decoder is modeled with SADF based FSM in order to solve problems of placing and scheduling this application on an embedded architecture. In the modeling step, a high-level performance analysis is performed to find an optimal balance between the decoding efficiency and the implementation cost, thereby reducing the complexity of the system. The case study in this case works with the HEVC/h.265 decoder that runs on the Xilinx Zedboard platform, which offers a real environment of experimentation.展开更多
为了保证一定视频质量下编码器输出的码率符合给定的目标码率,提出一种考虑视频内容特性的H.265/HEVC帧层码率分配算法。首先从率失真理论分析的角度推导出影响输出码率的主要因素,然后根据视频编码原理,预测出帧内容复杂度参数,从而建...为了保证一定视频质量下编码器输出的码率符合给定的目标码率,提出一种考虑视频内容特性的H.265/HEVC帧层码率分配算法。首先从率失真理论分析的角度推导出影响输出码率的主要因素,然后根据视频编码原理,预测出帧内容复杂度参数,从而建立一种更有效的帧层码率分配算法。实验结果表明,所提算法可以使帧层目标码率与编码码率保持更好的一致性,且重构视频质量平均提高了0.103 d B。展开更多
在H.265/HEVC基于R-λ模型码率控制算法中,为了提高最大编码单元(LCU)的比特分配的效果以及参数(α、β)更新的精度,提出一种码率控制优化算法。该算法主要是利用当前最大编码单元原始比特进行比特分配,以及利用编码失真度对参数(α、β...在H.265/HEVC基于R-λ模型码率控制算法中,为了提高最大编码单元(LCU)的比特分配的效果以及参数(α、β)更新的精度,提出一种码率控制优化算法。该算法主要是利用当前最大编码单元原始比特进行比特分配,以及利用编码失真度对参数(α、β)更新。实验结果表明,在恒定比特率情况下,相对于HM13.0码率控制算法三分量峰值信噪比(PSNR)增益至少提高0.76 d B,编码传输比特每帧消耗比特至少降低0.46%,编码时间至少减少0.54%。展开更多
Fractional motion estimation(FME) improves the video encoding efficiency significantly. However, its high computational complexity limits the real-time processing capability. Therefore, it is a key problem to reduce t...Fractional motion estimation(FME) improves the video encoding efficiency significantly. However, its high computational complexity limits the real-time processing capability. Therefore, it is a key problem to reduce the implementation complexity of FME, especially in hardware design. This paper presents a novel deeply pipelined interpolation architecture of FME for the real-time realization of H.265/HEVC full Ultra-HD video encoder. First, a pipelined interpolation architecture together with an elegant processing order is proposed to deal with different search positions in parallel without pipeline stall and data conflict. Second, interpolation results sharing strategies are exploited among search positions to reduce the memory cost. Finally, the structure of the interpolation filter is further optimized for an area efficient implementation. As a result, the proposed design costs 41 917 slice LUTs on the Xilinx Kintex-7 FPGA platform with a 308 MHz working frequency. The measured throughput reaches a record of 1.238 Gpixels/s, which is sufficient for the real-time encoding of 8192×4320@ 30 fps video.展开更多
文摘Multiprocessor System on Chip (MPSoC) technology presents an interesting solution to reduce the computational time of complex applications such as multimedia applications. Implementing the new High Efficiency Video Coding (HEVC/h.265) codec on the MPSoC architecture becomes an interesting research point that can reduce its algorithmic complexity and resolve the real time constraints. The implementation consists of a set of steps that compose the Co-design flow of an embedded system design process. One of the first anf key steps of a Co-design flow is the modeling phase which allows designers to make best architectural choices in order to meet user requirements and platform constraints. Multimedia applications such as HEVC decoder are complex applications that demand increasing degrees of agility and flexibility. These applications are usually modeling by dataflow techniques. Several extensions with several schedules techniques of dataflow model of computation have been proposed to support dynamic behavior changes while preserving static analyzability. In this paper, the HEVC/h.265 video decoder is modeled with SADF based FSM in order to solve problems of placing and scheduling this application on an embedded architecture. In the modeling step, a high-level performance analysis is performed to find an optimal balance between the decoding efficiency and the implementation cost, thereby reducing the complexity of the system. The case study in this case works with the HEVC/h.265 decoder that runs on the Xilinx Zedboard platform, which offers a real environment of experimentation.
文摘为了保证一定视频质量下编码器输出的码率符合给定的目标码率,提出一种考虑视频内容特性的H.265/HEVC帧层码率分配算法。首先从率失真理论分析的角度推导出影响输出码率的主要因素,然后根据视频编码原理,预测出帧内容复杂度参数,从而建立一种更有效的帧层码率分配算法。实验结果表明,所提算法可以使帧层目标码率与编码码率保持更好的一致性,且重构视频质量平均提高了0.103 d B。
文摘在H.265/HEVC基于R-λ模型码率控制算法中,为了提高最大编码单元(LCU)的比特分配的效果以及参数(α、β)更新的精度,提出一种码率控制优化算法。该算法主要是利用当前最大编码单元原始比特进行比特分配,以及利用编码失真度对参数(α、β)更新。实验结果表明,在恒定比特率情况下,相对于HM13.0码率控制算法三分量峰值信噪比(PSNR)增益至少提高0.76 d B,编码传输比特每帧消耗比特至少降低0.46%,编码时间至少减少0.54%。
基金Supported by the Zhejiang Provincial Natural Science Foundation of China(No.LQ15F010001,LY16F020029)the General Research Project of Zhejiang Provincial Education Department(No.Y201430479)
文摘Fractional motion estimation(FME) improves the video encoding efficiency significantly. However, its high computational complexity limits the real-time processing capability. Therefore, it is a key problem to reduce the implementation complexity of FME, especially in hardware design. This paper presents a novel deeply pipelined interpolation architecture of FME for the real-time realization of H.265/HEVC full Ultra-HD video encoder. First, a pipelined interpolation architecture together with an elegant processing order is proposed to deal with different search positions in parallel without pipeline stall and data conflict. Second, interpolation results sharing strategies are exploited among search positions to reduce the memory cost. Finally, the structure of the interpolation filter is further optimized for an area efficient implementation. As a result, the proposed design costs 41 917 slice LUTs on the Xilinx Kintex-7 FPGA platform with a 308 MHz working frequency. The measured throughput reaches a record of 1.238 Gpixels/s, which is sufficient for the real-time encoding of 8192×4320@ 30 fps video.
