精密的时间作为科研和工程技术等方面的基本物理参量，其测量的基本手段是精密时间一数字转换电路（Time—to-Time Digital Converter，简称TDC）．当前主流的TDC实现方法（“粗”时间测量加”细”时间测量）能达到亚纳秒的时间分辨率...精密的时间作为科研和工程技术等方面的基本物理参量，其测量的基本手段是精密时间一数字转换电路（Time—to-Time Digital Converter，简称TDC）．当前主流的TDC实现方法（“粗”时间测量加”细”时间测量）能达到亚纳秒的时间分辨率，但很难实现一致性很好的精确时间延时，误差较大．基于FPGA具有丰富专用进位连线的资源，对利用现场可编程逻辑器件FPGA中的专用进位连线实现时间内插链，从而实现精密TDC设计，灵活性好，成本低．并对TDC进行了时序仿真，测量的精度可达70ps，取得了一致性很好的精确时间延时．展开更多
In this paper,we report the electronics of a timing measurement system of PTB(portable TDC board), which is a handy tool based on USB interface,customized for high precision time measurements without any crates. The t...In this paper,we report the electronics of a timing measurement system of PTB(portable TDC board), which is a handy tool based on USB interface,customized for high precision time measurements without any crates. The time digitization is based on the High Performance TDC Chip(HPTDC).The real-time compensation for HPTDC outputs and the USB master logic are implemented in an ALTERA's Cyclone FPGA.The architecture design and logic design are described in detail.Test of the system showed a time resolution of 13.3 ps.展开更多
A novel front-end circuit designed for PMT signals processing considering the solution of "Time Walk" correction is discussed in this paper. We are trying to apply the TOT (Time over Threshold) technique to ...A novel front-end circuit designed for PMT signals processing considering the solution of "Time Walk" correction is discussed in this paper. We are trying to apply the TOT (Time over Threshold) technique to our research. Different from traditional ways, where amplitude is measured, time width is measured for slew correction here, which takes the advantage of TDC. Expensive fast ADCs are abandoned and the whole time measurement electronics design becomes more effective and economical. Test boards have been developed and a convenient method is introduced to evaluate our TOT technique. Results have shown that a 10ps slew correction resolution is achieved throughout the amplitude range from -108mV to -2000mV for negative signals of both 5 ns leading and trailing edge with 10 ns 50%-50% pulse width.展开更多
The impact of the integral non-linearity (INL) to the time resolution of HPTDC (High Performance Time to Digital Converter) is presented in this paper.An INL correction method based on look-up table (LUT),is proposed ...The impact of the integral non-linearity (INL) to the time resolution of HPTDC (High Performance Time to Digital Converter) is presented in this paper.An INL correction method based on look-up table (LUT),is proposed to minimize such INL and improve the time resolution.This scheme is implemented in a single Field Programmable Gate Array (FPGA) device for real-time compensation.The INL characteristic estimation is based on a statistical approach,in which a sufficiently large number of random input signals are measured.The prototype tests show that the deviation for time resolution due to INL can be reduced greatly,from more than 80 ps to less than 20 ps,which can meet the requirement of BES (Beijing Spectrometer) III Time-Of-Flight detector.展开更多
作为北京谱仪(Beijing Spectrometer,简称BES)的改造,BESⅢ将把TOF(time-of-flight)测量精度提高到一个新的水平,总时间分辨不大于90ps．其中要求前端电子学(Front End Electronics,FEE)对时间测量的不确定性贡献小于25ps．本文介绍了TO...作为北京谱仪(Beijing Spectrometer,简称BES)的改造,BESⅢ将把TOF(time-of-flight)测量精度提高到一个新的水平,总时间分辨不大于90ps．其中要求前端电子学(Front End Electronics,FEE)对时间测量的不确定性贡献小于25ps．本文介绍了TOF前端读出电子学系统原型电路的设计和初步的测试结果．展开更多
文摘精密的时间作为科研和工程技术等方面的基本物理参量，其测量的基本手段是精密时间一数字转换电路（Time—to-Time Digital Converter，简称TDC）．当前主流的TDC实现方法（“粗”时间测量加”细”时间测量）能达到亚纳秒的时间分辨率，但很难实现一致性很好的精确时间延时，误差较大．基于FPGA具有丰富专用进位连线的资源，对利用现场可编程逻辑器件FPGA中的专用进位连线实现时间内插链，从而实现精密TDC设计，灵活性好，成本低．并对TDC进行了时序仿真，测量的精度可达70ps，取得了一致性很好的精确时间延时．
基金Supported by the National Natural Science Foundation of China(Grant No.10775133)
文摘In this paper,we report the electronics of a timing measurement system of PTB(portable TDC board), which is a handy tool based on USB interface,customized for high precision time measurements without any crates. The time digitization is based on the High Performance TDC Chip(HPTDC).The real-time compensation for HPTDC outputs and the USB master logic are implemented in an ALTERA's Cyclone FPGA.The architecture design and logic design are described in detail.Test of the system showed a time resolution of 13.3 ps.
基金Supported by National Natural Science Foundation of China (10405023)National Large-Scale Science Project BEPCII
文摘A novel front-end circuit designed for PMT signals processing considering the solution of "Time Walk" correction is discussed in this paper. We are trying to apply the TOT (Time over Threshold) technique to our research. Different from traditional ways, where amplitude is measured, time width is measured for slew correction here, which takes the advantage of TDC. Expensive fast ADCs are abandoned and the whole time measurement electronics design becomes more effective and economical. Test boards have been developed and a convenient method is introduced to evaluate our TOT technique. Results have shown that a 10ps slew correction resolution is achieved throughout the amplitude range from -108mV to -2000mV for negative signals of both 5 ns leading and trailing edge with 10 ns 50%-50% pulse width.
基金Supported by BEPCII project (BEPC II-UDDETF-309-HT182/2004)Knowledge Innovation Program of The Chinese Academy of Sciences (YFKJCX3. SYW. N5)the National Natural Science Foundation of China (No.10970033)
文摘The impact of the integral non-linearity (INL) to the time resolution of HPTDC (High Performance Time to Digital Converter) is presented in this paper.An INL correction method based on look-up table (LUT),is proposed to minimize such INL and improve the time resolution.This scheme is implemented in a single Field Programmable Gate Array (FPGA) device for real-time compensation.The INL characteristic estimation is based on a statistical approach,in which a sufficiently large number of random input signals are measured.The prototype tests show that the deviation for time resolution due to INL can be reduced greatly,from more than 80 ps to less than 20 ps,which can meet the requirement of BES (Beijing Spectrometer) III Time-Of-Flight detector.
文摘作为北京谱仪(Beijing Spectrometer,简称BES)的改造,BESⅢ将把TOF(time-of-flight)测量精度提高到一个新的水平,总时间分辨不大于90ps．其中要求前端电子学(Front End Electronics,FEE)对时间测量的不确定性贡献小于25ps．本文介绍了TOF前端读出电子学系统原型电路的设计和初步的测试结果．
