提出了一种基于随电流变化的铁芯电感的磁通门HSPICE(High Simulation Program with IC Emphasis)模型,该磁通门模型铁芯的磁滞回线使用反正切函数来描述,其激励与测量线圈等效为一种随电流变化的电感电路模型。本文给出了全电路元件的...提出了一种基于随电流变化的铁芯电感的磁通门HSPICE(High Simulation Program with IC Emphasis)模型,该磁通门模型铁芯的磁滞回线使用反正切函数来描述,其激励与测量线圈等效为一种随电流变化的电感电路模型。本文给出了全电路元件的磁通门模型的参数及提取方法,此模型可以在任意形状的电压激励波形下仿真,与已有的磁通门模型相比,具有仿真精度高、需要参数少且计算容易和可以方便进行输出信号处理的特点。实验和仿真结果对比表明,双铁芯磁通门HSPICE模型仿真的输入电流和输出电压的幅值分别为146 m A和1.03 V,与实际测试的146.6 m A和1.177 V相比,输入电流有0.6 m A的误差,输出电压有0.147 V的误差。展开更多
为在HSPICE中建立一种计算简单且精度较高的碳纳米管场效应管(carbon nanotube field effect transistor,CNTFET)模型,在CNTFET半经典建模方法的基础上,分析了自洽电势与载流子密度之间的关系,提出用线性近似进行拟合,并推导了自洽电势...为在HSPICE中建立一种计算简单且精度较高的碳纳米管场效应管(carbon nanotube field effect transistor,CNTFET)模型,在CNTFET半经典建模方法的基础上,分析了自洽电势与载流子密度之间的关系,提出用线性近似进行拟合,并推导了自洽电势的显式表达式,从而避免了积分方程的迭代求解过程.然后在HSPICE中建立了相应的CNTFET模型,通过仿真比较,结果表明该模型具有较高的精度,用其构建的逻辑门电路能够实现相应逻辑功能,且运算时间大为减少.展开更多
This paper proposes an equivalent circuit model to analyze the reason for the dispersion of sub-threshold current （also known as zero-current point dispersion） in organic thin-film transistors. Based on the level 61...This paper proposes an equivalent circuit model to analyze the reason for the dispersion of sub-threshold current （also known as zero-current point dispersion） in organic thin-film transistors. Based on the level 61 amorphous silicon thin-film transistor model in star-HSPICE, the results from our equivalent circuit model simulation reveal that zero-current point dispersion can be attributed to two factors： large contact resistance and small gate resistance. Furthermore, it is found that decreasing the contact resistance and increasing the gate resistance can efficiently reduce the dispersion. If the contact resistance can be controlled to 0 g2, all the zero-current points can gather together at the base point. A large gate resistance is good for constraining the dispersion of the zero-current points and gate leakage. The variances of the zero-current points are 0.0057 and nearly 0 when the gate resistances are 17 MΩ and 276 MΩ, respectively.展开更多
文摘提出了一种基于随电流变化的铁芯电感的磁通门HSPICE(High Simulation Program with IC Emphasis)模型,该磁通门模型铁芯的磁滞回线使用反正切函数来描述,其激励与测量线圈等效为一种随电流变化的电感电路模型。本文给出了全电路元件的磁通门模型的参数及提取方法,此模型可以在任意形状的电压激励波形下仿真,与已有的磁通门模型相比,具有仿真精度高、需要参数少且计算容易和可以方便进行输出信号处理的特点。实验和仿真结果对比表明,双铁芯磁通门HSPICE模型仿真的输入电流和输出电压的幅值分别为146 m A和1.03 V,与实际测试的146.6 m A和1.177 V相比,输入电流有0.6 m A的误差,输出电压有0.147 V的误差。
文摘为在HSPICE中建立一种计算简单且精度较高的碳纳米管场效应管(carbon nanotube field effect transistor,CNTFET)模型,在CNTFET半经典建模方法的基础上,分析了自洽电势与载流子密度之间的关系,提出用线性近似进行拟合,并推导了自洽电势的显式表达式,从而避免了积分方程的迭代求解过程.然后在HSPICE中建立了相应的CNTFET模型,通过仿真比较,结果表明该模型具有较高的精度,用其构建的逻辑门电路能够实现相应逻辑功能,且运算时间大为减少.
文摘This paper proposes an equivalent circuit model to analyze the reason for the dispersion of sub-threshold current （also known as zero-current point dispersion） in organic thin-film transistors. Based on the level 61 amorphous silicon thin-film transistor model in star-HSPICE, the results from our equivalent circuit model simulation reveal that zero-current point dispersion can be attributed to two factors： large contact resistance and small gate resistance. Furthermore, it is found that decreasing the contact resistance and increasing the gate resistance can efficiently reduce the dispersion. If the contact resistance can be controlled to 0 g2, all the zero-current points can gather together at the base point. A large gate resistance is good for constraining the dispersion of the zero-current points and gate leakage. The variances of the zero-current points are 0.0057 and nearly 0 when the gate resistances are 17 MΩ and 276 MΩ, respectively.
