This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended ...This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes.展开更多
The undetected error probability and error detection capability of shortened Hamming codes and their dual codes are studied in this paper. We also obtain some interesting properties for the shortened Simplex codes.
We study the representations of code vertex operator superalgebras resulting from a binary linear code which contains codewords of odd weight. We also show that there exists only one set of seven mutually orthogonal c...We study the representations of code vertex operator superalgebras resulting from a binary linear code which contains codewords of odd weight. We also show that there exists only one set of seven mutually orthogonal conformal vectors with central charge 1/2 in the Hamming code vertex operator superalgebra MH7. Phrthermore, we classify all the irreducible weak MH7-modules.展开更多
Embedded RAM blocks（BRAMs） in field programmable gate arrays（FPGAs） are susceptible to single event effects（SEEs） induced by environmental factors such as cosmic rays, heavy ions, alpha particles and so on. As t...Embedded RAM blocks（BRAMs） in field programmable gate arrays（FPGAs） are susceptible to single event effects（SEEs） induced by environmental factors such as cosmic rays, heavy ions, alpha particles and so on. As technology scales, the issue will be more serious. In order to tackle this issue, two different error correcting codes（ECCs）, the shortened Hamming codes and shortened BCH codes, are investigated in this paper. The concrete design methods of the codes are presented. Also, the codes are both implemented in flash-based FPGAs. Finally, the synthesis report and simulation results are presented in the paper. Moreover, heavy-ion experiments are performed,and the experimental results indicate that the error cross-section of the device using the shortened Hamming codes can be reduced by two orders of magnitude compared with the device without mitigation, and no errors are discovered in the experiments for the device using the shortened BCH codes.展开更多
基金Sponsored by the Opening Project of National Key Laboratory of Science and Technology on Reliability PhysicsApplication Technology of Electrical Component(Grant No.ZHD200903)
文摘This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes.
基金supported by the National Natural Science Foundation of China, No. 69802008.
文摘The undetected error probability and error detection capability of shortened Hamming codes and their dual codes are studied in this paper. We also obtain some interesting properties for the shortened Simplex codes.
文摘We study the representations of code vertex operator superalgebras resulting from a binary linear code which contains codewords of odd weight. We also show that there exists only one set of seven mutually orthogonal conformal vectors with central charge 1/2 in the Hamming code vertex operator superalgebra MH7. Phrthermore, we classify all the irreducible weak MH7-modules.
基金Supported by National Natural Science Foundation of China(11079045,11179003 and 11305233)
文摘Embedded RAM blocks（BRAMs） in field programmable gate arrays（FPGAs） are susceptible to single event effects（SEEs） induced by environmental factors such as cosmic rays, heavy ions, alpha particles and so on. As technology scales, the issue will be more serious. In order to tackle this issue, two different error correcting codes（ECCs）, the shortened Hamming codes and shortened BCH codes, are investigated in this paper. The concrete design methods of the codes are presented. Also, the codes are both implemented in flash-based FPGAs. Finally, the synthesis report and simulation results are presented in the paper. Moreover, heavy-ion experiments are performed,and the experimental results indicate that the error cross-section of the device using the shortened Hamming codes can be reduced by two orders of magnitude compared with the device without mitigation, and no errors are discovered in the experiments for the device using the shortened BCH codes.
