Study on Hardening and Reuse Technology of Drilling Waste

In order to meet the increasingly strict environmental requirements and achieve the comprehensive utilization of waste in drilling operation,three techniques were used to harden the drilling waste.The three techniques are cement hardening technology,fly ash hardening technology and quicklime-sodium silicate hardening technology.Orthogonal analysis was used to evaluate and optimize the experimental results from the three techniques.The results show that the hardening system of quicklime-sodium silicate is not satisfying,and the compressive strength of hardened body is only 1.32 MPa.The optimal mass ratio in cement hardening system is drilling waste∶water∶YHJ1∶YHJ2∶YHJ3∶cement = 10∶4∶3.2∶2.2∶0.5∶4.The optimal mass ratio in fly ash hardening system is drilling waste∶water∶YHJ1∶YHJ2∶YHJ3∶fly ash = 10∶4∶3.2∶1.8∶1.5∶2.The compressive strength reaches 3.19 and 2.95 MPa respectively.Based on this strength,the hardened body can be used as low-strength building bricks,subgrade or nutrition bowls in arid regions to achieve the reuse of drilling waste.

Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.