An efficient adapting virtual intermediate instruction set towards optimized dynamic binary translator (DBT) system

A new efficient adapting virtual intermediate instruction set,V-IIS,is designed and implemented towards the optimized dynamic binary translator (DBT) system.With the help of this powerful but previously little-studied component,DBTs can not only get rid of the dependence of machine(s),but also get better performance.From our systematical study and evaluation,experimental results demonstrate that if V-IIS is well designed,without affecting the other optimizing measures,this could make DBT's performance close to those who do not have intermediate instructions.This study is an important step towards the grand goal of high performance "multi-source" and "multi-target" dynamic binary translation.

UNI-SPEC:An Instruction Set Description Language

Microprocessor development emphasizes hardware and software co design. Hw/Sw co design is a modern technique aimed at shortening the time to market in designing the real time and embedded systems. Key feature of this approach is simultaneous development of the program tools and the target processor to match software application. An effective co design flow must therefore support automatic software toolkits generation, without loss of optimizing efficiency. This has resulted in a paradigm shift towards a language based design methodology for microprocessor optimization and exploration. This paper proposes a formal grammar, UNI SPEC, which supports the automatic generation of assemblers, to describe the translation rules from assembly to binary. Based on UNI SPEC, it implements two typical applications, i.e., automatically generating the assembler and the test suites.

Analyzing and Seeking Minimum Test Instruction Set of Digital Signal Processor for Motor Control

The relativity of instructions of motor control digital signal processor (MCDSP) in the design is analyzed. A method for obtaining a minimum instruction set in plac e of the complete instruction set during generation of testing procedures is giv en in terms of the processor presentation matrix between micro-operators and in structions of MCDSP.

Verification of instruction set specification for an ASIP

In order to gain the great performance of ASIP, this paper discusses different aspects of an ASIP instruction set specification like syntax, encoding, constraints as welt as behaviors, and introduces our ADL model based methodology to check them. The automatic generation of test cases based on our straight-forward instruction representation is shown, and the efficient generation of them with good coverage is shown as well. The verification of the constraint checker, a very important tool for programmer, is performed. Results show that the toolkit can find some errors in previous delivery tools, and the introduced methodology verifies the feasibility of our instruction set specification.

面向向量部件的指数和对数函数优化方法

指数和对数函数是浮点计算中重要的超越函数,在不同应用领域使用广泛。现代处理器向量寄存器宽度呈现逐代增加的趋势,为了进一步提高上层应用对向量部件的利用率,研究向量指数和对数函数优化方法具有重要的科学价值和现实意义。针对现有向量函数实现的性能瓶颈,设计和实现了面向向量部件的指数和对数函数优化方法,包括基于硬件加速指令的向量查表优化、分支优化和精度性能取舍优化。模拟器上的实验表明,优化实现的向量指数和对数函数均达到业界高精度标准,函数性能优于当前最佳开源实现,加速比达1.44以上。真实应用测试进一步表明,应用程序在优化的向量函数支持下可以实现高效向量化,相比原始标量实现平均性能提升达2.53倍。

基于SystemC的SoC行为级软硬件协同设计

针对目前SoC设计中存在的软硬件协同验证的时间瓶颈问题,提出了一种使用系统建模语言SystemC对SoC进行总线周期精确行为级建模的方法,采用该方法构建SoC芯片总线周期精确行为级模型进行前期验证。该模型基于32位RISC构建,并可配置其它硬件模块。实验结果表明:模型完全仿真实际硬件电路,所有的接口信号在系统时钟的任一时刻被监测和分析,很大程度地提高了仿真速度,并且可以在前期作系统的软硬件协同仿真和验证,有效地缩短了目前SoC芯片设计中在RTL级作软硬件协同仿真验证时的时间开销。

NA-ROB:基于RISC-V超标量处理器的改进

重排序缓存(ROB)是超标量处理器中的重要模块,用于确保乱序执行的指令能够正确地完成和提交。然而,在大规模超标量处理器中,存在ROB阻塞以及ROB容量有限的问题。为了解决上述问题并提高处理器性能,提出了零寄存器分配策略,通过将没有目的寄存器的指令单独存储来避免占用ROB表项。同时,引入容量可动态调整的缓存结构(AROB),将长延时指令与普通指令分别存储在ROB和AROB中,以降低长延时指令导致的阻塞。改进后的超标量处理器被命名为NA-ROB,经过SPEC 2006基准测试程序的实验评估,结果表明,NA-ROB超标量处理器相比于传统的ROB超标量处理器,平均IPC提升了66%,同时ROB的阻塞概率降低了48%。因此,所提出的改进方法显著提升了处理器的整体性能和效率。

SystemC2.0的事务级建模

采用SystemC2.0,结合AMBA片上总线,探讨了在事务级的建模方法,并结合JPEG2000中的无损小波提升算法给出建模实例。介绍了SystemC2.0通过指令集模拟器建立事务级处理器模型的一般方法和步骤。

基于SystemC和ISS的软硬件协同验证方法

随着SoC的出现和发展,软硬件协同验证已经成为当前的研究热点。本文对传统的基于ISS的软硬件协同验证方法进行改进,提出了一种基于SystemC和ISS的软硬件协同验证方法。该方法使用SystemC分别对系统进行事务级、寄存器传输级的建模,在系统验证早期进行无时序的软硬件协同验证,后期进行时钟精确的软硬件协同验证,并对仿真速度进行了优化。同传统的基于ISS的软硬件协同验证方法相比,该方法保证了软硬件的并行开发,且仿真速度快、调试方便,是一种高效、高重用性的软硬件协同验证方法。

基于指令扩展的RISC-V可配置故障注入检测方法

针对处理器运行时受到故障攻击出现的数据流错误,提出了一种面向RISC-V处理器微架构的模式可配置故障注入检测方法。该方法基于RISC-V指令集架构,利用其可扩展性添加带模式配置的自定义算术逻辑运算指令和控制与状态寄存器,以软硬件结合的方式同时实现算术逻辑运算和故障注入检测。在软件层面,通过写寄存器指令将配置信息写入自定义的控制与状态寄存器,配置自定义指令的故障注入检测模式,包括信息冗余和时间冗余2种故障注入检测模式及其参数;在硬件层面,实现了支持模式可配置故障注入检测方法的RISC-V处理器微架构。采用仿真器命令模拟故障注入,验证扩展后的RISC-V处理器的功能正确性与故障注入检测能力。实验结果表明:当信息冗余模式和时间冗余模式的应用频率相同时,模式可配置方法相较于单信息冗余方法,平均故障检测率提高13.34%,引入4.4%的平均资源开销;相较于单时间冗余方法,降低了8.24%的平均时间开销,故障检测率降低了13.33%。所提模式可配置方法可以实现故障检测率和时间开销的折中,适用于不同安全性和性能需求的应用场景。

基于SystemC的多核指令集模拟器并行化技术

多核指令集模拟器一直是指令集模拟器的研究热点。如何有效,快速的对多核指令集进行模拟,成为了设计多核模拟器的难点。本文描述了一种基于SystemC TLM框架的多核指令集模拟技术。在利用SystemC易于建模的优点的同时克服了其模块之间串行调度的缺点,实现了基于SystemC的并行多核模拟器。

高校人力资源管理专业人才培养模式的优化策略

为优化高校人力资源管理专业的人才培养模式,从而提升学生的综合素质及实践能力,在问卷数据的基础上开展信度与主成分分析,讨论培养模式的侧重点。结果显示,问卷数据具有高可靠性,能为研究提供稳定的数据基础。主成分分析提取了4个主成分,即课程设置、职业发展与就业、实践实习、教学设计,这4个因素在人才培养模式中发挥着关键作用。基于此,高校应优化课程体系,加强与企业合作,通过建立稳定的实习基地与实践平台增加学生的实际操作机会,以推动高校人才培养模式的创新与改革,提升学生的就业竞争力与社会适应能力。

Research on rapid development platform of PLC control system

In the field of industrial process control,a fast-development platform for programmable logic controller(PLC)systems is designed in order to solve two main problems of rapid development of PLC control system and programmability of controlling software.In the aspect of design,the platform is composed of hardware controlling and software monitoring and is taking industrial computer as the core.Under the Windows environment,the platform establishes the control instruction set,develops the configuration function and visual programming function of the monitoring software and it integrates PLC controller based on Visual Basic software.In order to achieve the function of data monitoring,it has realized the serial communication between computer and PLC by using RS-485 and RS-232 serial ports line communication.The platform designs the intelligent instruction scheduling strategy by studying the encoding and decoding rules of the communication instruction set.It proposes a method for rapidly developing control programs by adopting the expert control mode,which enables clients to develop and modify programs conveniently by importing instructions in a non-coded manner.After experimental testing,the platform is proved successful achieving both the rapid development of PLC control system and the rapid modification of monitoring software.

Hardware-Software Co-Simulation for SOC Functional Verification

A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program--the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.

A TSE based design for MMSE and QRD of MIMO systems based on ASIP

A Taylor series expansion(TSE) based design for minimum mean-square error(MMSE) and QR decomposition(QRD) of multi-input and multi-output(MIMO) systems is proposed based on application specific instruction set processor(ASIP), which uses TSE algorithm instead of resource-consuming reciprocal and reciprocal square root(RSR) operations.The aim is to give a high performance implementation for MMSE and QRD in one programmable platform simultaneously.Furthermore, instruction set architecture(ISA) and the allocation of data paths in single instruction multiple data-very long instruction word(SIMD-VLIW) architecture are provided, offering more data parallelism and instruction parallelism for different dimension matrices and operation types.Meanwhile, multiple level numerical precision can be achieved with flexible table size and expansion order in TSE ISA.The ASIP has been implemented to a 28 nm CMOS process and frequency reaches 800 MHz.Experimental results show that the proposed design provides perfect numerical precision within the fixed bit-width of the ASIP, higher matrix processing rate better than the requirements of 5G system and more rate-area efficiency comparable with ASIC implementations.

A wireless endoscope based on an embedded system

We presented a wireless endoscope system developed on the embedded Linux platform. This wireless endoscope system consists of three parts: the endoscope capsule,the portable equipment and the image workstation,which make this system wireless and portable. Hardware design of this system and software design of the portable equipment are described. In clinical use,patients swallow the endoscope capsule for gastrointestinal inspection. The portable equipment receives images of gastrointestinal tract via the radio frequency module while it sets and reads back parameters of the capsule via the low frequency module. Acquired image data can be saved as a FAT32 format file in an universal serial bus disk. Images can be processed and reviewed at an Microsoft Windows PC workstation in the next stage. The image acquired by this wireless endoscope system is quite effective with clear details of gastrointestinal tract. However,the endoscope capsule was large,making it difficult to swallow. So the printed circuit board design of endoscope capsule needs to be improved.

基于System C的多处理器片上系统软硬件协同仿真

给出了基于SystemC的处理器片上系统(System On a Chip)的协同仿真的两种方法。并通过对系统的仿真,对两个方法进行了对比,给出了在仿真间隔时间、速度和其他性能之间的比较。对目前SOC的软硬件协同设计验证有一定的实际意义。

Internet-Based Technologies for Design of Embedded Systems

In recent years, online engineering technologies are widely distributed and developed. Their influence on society is very strong. The Internet technology has provided additional opportunities for a new development level of education, design and production. Associations and scientific conferences in the field of online engineering that appeared, seek to foster practices in education and research in higher education institutions and the industry on online engineering. A particular challenge for online engineering is how to extend the traditional equipments and laboratories to the Internet. A method of the embedded systems design with using online laboratory is described in this paper. Also, in this paper the experimental set of remote laboratory which allows carrying out hardware/software oriented design of the embedded control system of a mobile platform is considered.

面向SIMD指令集的SM4算法比特切片优化

SM4算法是中国自主设计的商用分组密码算法,其加解密计算性能成为影响信息系统数据机密性保障的重要因素之一.现有SM4算法优化主要面向硬件设计和软件查表等方向展开研究,分别存在依赖特定硬件环境、效率低下且易遭受侧信道攻击等问题.比特切片技术通过对输入数据重组实现了并行化高效分组密码处理,可以抵御针对缓存的侧信道攻击.然而现有切片分组密码研究对硬件平台相关性强、处理器架构支持单一,并且并行化处理流水启动较慢,面向小规模数据的加解密操作难以充分发挥单指令多数据(single instruction multiple data,SIMD)等先进指令集的优势.针对上述问题,首先提出了一种跨平台的通用切片分组密码算法模型,支持面向不同的处理器指令字长提供一致化的通用数据切片方法.在此基础上,提出了一种面向SIMD指令集的细粒度切片并行处理SM4优化算法,通过细粒度明文切片重组与线性处理优化有效缩短算法启动时间.实验结果表明,相比通用SM4算法,优化的SM4比特切片算法加密速率最高可达438.0 MBps,加密每字节所需的时钟周期最快高达7.0 CPB(cycle/B),加密性能平均提升80.4%~430.3%.

智能时代下计算机系统结构课程的重构与教学设计

智能时代下信息技术的加速演化对计算机专业人才培养的目标和模式提出变革诉求。从计算机系统结构课程出发,总结建设过程中培养学生软硬件协同的计算机系统能力的思路、举措以及成效。对教学内容和实践项目进行重构,实现经典体系结构与智能系统的交叉融合、课程思政与教学内容的深度融合,取得显著的成效,推动计算机系统能力培养的内容和形式变革。课程经验可被推广至其他课程,以实现计算机专业课以及新工科课程的改造升级。