Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an impro...Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desaturation algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits a higher fault coverage than other algorithms with Tests on some benchmarks show that the algorithm gives less area overhead and even less time delay.展开更多
Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on...Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on mobility scheduling, in which the scheduling begins from the operation with least mobility. In our data path scheduling scheme, the lifetimes of the I/O variables are made as short as possible to enlarge the possibility of the intermediate variables being allocated to the I/O registers. In this way, the controllability/observability of the intermediate variables can be improved. Combined with a weighted graph-based register allocation method, this scheme can obtain better testability. Experimental results on some benchmarks and example circuits show that the proposed scheme can get higher fault coverage compared with other scheduling schemes at little area overhead and even less time delay.展开更多
基金Supported by the National Key Basic Research and Development(973) Program of China (No. 2005CB321604)the National Natural Science Foundation of China (No. 60633060)
文摘Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desaturation algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits a higher fault coverage than other algorithms with Tests on some benchmarks show that the algorithm gives less area overhead and even less time delay.
基金the National Key Basic Research and Development (973) of China (No. 2005CB321604)the National Natural Science Foundation of China (No. 60633060)
文摘Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on mobility scheduling, in which the scheduling begins from the operation with least mobility. In our data path scheduling scheme, the lifetimes of the I/O variables are made as short as possible to enlarge the possibility of the intermediate variables being allocated to the I/O registers. In this way, the controllability/observability of the intermediate variables can be improved. Combined with a weighted graph-based register allocation method, this scheme can obtain better testability. Experimental results on some benchmarks and example circuits show that the proposed scheme can get higher fault coverage compared with other scheduling schemes at little area overhead and even less time delay.
