Technical Decisions on Several Key Problems in VHDLHigh Level Synthesis System

This paper studies the realization of the high level synthesis fromsystem behavioral (algorithmic or functional) description of circuits to structuraldescription of RTL and logic level. Based on Xilinx-FPGA libraryl the structural description is mapped to technology-dependent ASIC, and FPGA chips are generated.The main points in this paper include the technical decision of each subsystem in aVHDL high level synthesis system HLS/BIT. The system is realized on SUN SPARC2, and correct running results are given.

基于HLS的矩阵求逆算法设计优化

本文主要研究了HLS多层动态边界循环的优化策略。HLS利用C/C++语言完成算法设计和验证,通过高级综合工具自动生成RTL代码,显著缩短了算法FPGA设计复杂度及实现效率,在信号处理算法实现方面有着显著的优势。但对于具有多层动态循环边界的算法,由于各层循环的数据依赖性及循环边界的不可预知性,HLS难以实现理想的结果。本文以Cholesky分解矩阵求逆算法为例,通过对矩阵求逆计算过程数据计算顺序、数据依赖性、运算步骤进行了分析与理论计算,提出了一种将多层循环优化为单层、两层循环的方法,解决了流水线优化指令高效应用问题。实现结果表明,经过优化后,在资源增加较少的情况下,矩阵求逆延迟性能提升118倍。