A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase...A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.展开更多
This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The ...This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.展开更多
设计实现了一种带参考通道的时间交叉ADC(TIADC)通道误差数字后台实时校准方法。参考通道ADC与TIADC各个子通道ADC依次对齐,对同一输入信号在同一时刻进行采样并转换,输出差值被用在数字后台LMS自适应校准算法中以计算通道间的失配误差...设计实现了一种带参考通道的时间交叉ADC(TIADC)通道误差数字后台实时校准方法。参考通道ADC与TIADC各个子通道ADC依次对齐,对同一输入信号在同一时刻进行采样并转换,输出差值被用在数字后台LMS自适应校准算法中以计算通道间的失配误差估计值,实现对各通道失调失配、增益失配和采样时刻失配造成误差的实时校准。FPGA实验结果表明,应用于12 bit,4通道,采样频率400 MS/s的TIADC中,归一化输入频率fin/fs=0.134时,在失调误差、增益误差和采样时钟误差分别为5%FSR、5%和1%Ts条件下,校准后信号噪声失真比(SNR)和无杂散动态范围(SFDR)分别提高了约19.61 d B和28.28 d B,为73.83 d B和86.15 d B,有效位达到11.96位。本校准方法计算复杂度低、易于硬件实现,能够应用于任意通道数的TIADC校准。展开更多
基金Supported by National Natural Science Foundation of China (No.60806010,No.60976030)
文摘A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.
文摘This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.
文摘设计实现了一种带参考通道的时间交叉ADC(TIADC)通道误差数字后台实时校准方法。参考通道ADC与TIADC各个子通道ADC依次对齐,对同一输入信号在同一时刻进行采样并转换,输出差值被用在数字后台LMS自适应校准算法中以计算通道间的失配误差估计值,实现对各通道失调失配、增益失配和采样时刻失配造成误差的实时校准。FPGA实验结果表明,应用于12 bit,4通道,采样频率400 MS/s的TIADC中,归一化输入频率fin/fs=0.134时,在失调误差、增益误差和采样时钟误差分别为5%FSR、5%和1%Ts条件下,校准后信号噪声失真比(SNR)和无杂散动态范围(SFDR)分别提高了约19.61 d B和28.28 d B,为73.83 d B和86.15 d B,有效位达到11.96位。本校准方法计算复杂度低、易于硬件实现,能够应用于任意通道数的TIADC校准。
