A High Speed,12-Channel Parallel,Monolithic Integrated CMOS OEIC Receiver

The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit （OEIC） receiver are reported. Each channel of the receiver consists of a photodetector, a transimpedance amplifier,and a post-amplifier. The double photodiode structure speeds up the receiver but hinders responsivity. The adoption of active inductors in the TIA circuit extends the - 3dB bandwidth to a higher level. The receiver has been realized in a CSMC 0.6μm standard CMOS process. The measured results show that a single channel of the receiver is able to work at bit rates of 0.8- 1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

Dynamic Performance of High Speed Solenoid Valve with Parallel Coils

The methods of improving the dynamic performance of high speed on/off solenoid valve include increasing the magnetic force of armature and the slew rate of coil current, decreasing the mass and stroke of moving parts. The increase of magnetic force usually leads to the decrease of current slew rate, which could increase the delay time of the dynamic response of solenoid valve. Using a high voltage to drive coil can solve this contradiction, but a high driving voltage can also lead to more cost and a decrease of safety and reliability. In this paper, a new scheme of parallel coils is investigated, in which the single coil of solenoid is replaced by parallel coils with same ampere turns. Based on the mathematic model of high speed solenoid valve, the theoretical formula for the delay time of solenoid valve is deduced. Both the theoretical analysis and the dynamic simulation show that the effect of dividing a single coil into N parallel sub-coils is close to that of driving the single coil with N times of the original driving voltage as far as the delay time of solenoid valve is concerned. A specific test bench is designed to measure the dynamic performance of high speed on/off solenoid valve. The experimental results also prove that both the delay time and switching time of the solenoid valves can be decreased greatly by adopting the parallel coil scheme. This research presents a simple and practical method to improve the dynamic performance of high speed on/off solenoid valve.

Dynamic Analysis of High-Speed Boat Motion Simulator by a Novel 3-DoF Parallel Mechanism with Prismatic Actuators Based on Seakeeping Trial

In this study,we focused on a novel parallel mechanism for utilizing the motion simulator of a high-speed boat(HSB).First,we expressed the real behavior of the HSB based on a seakeeping trial.For this purpose,we recorded the motion parameters of the HSB by gyroscope and accelerometer sensors,while using a special data acquisition technique.Additionally,a Chebychev highpass filter was applied as a noise filter to the accelerometer sensor.Then,a novel 3 degrees of freedom(DoF)parallel mechanism(1T2R)with prismatic actuators is proposed and analyses were performed on its inverse kinematics,velocity,and acceleration.Finally,the inverse dynamic analysis is presented by the principle of virtual work,and the validation of the analytical equations was compared by the ADAMS simulation software package.Additionally,according to the recorded experimental data of the HSB,the feasibility of the proposed novel parallel mechanism motion simulator of the HSB,as well as the necessity of using of the washout filters,was explored.

Development of a Novel Parallel-spool Pilot Operated High-pressure Solenoid Valve with High Flow Rate and High Speed

High-pressure solenoid valve with high flow rate and high speed is a key component in an underwater driving system.However,traditional single spool pilot operated valve cannot meet the demands of both high flow rate and high speed simultaneously.A new structure for a high pressure solenoid valve is needed to meet the demand of the underwater driving system.A novel parallel-spool pilot operated high-pressure solenoid valve is proposed to overcome the drawback of the current single spool design.Mathematical models of the opening process and flow rate of the valve are established.Opening response time of the valve is subdivided into 4 parts to analyze the properties of the opening response.Corresponding formulas to solve 4 parts of the response time are derived.Key factors that influence the opening response time are analyzed.According to the mathematical model of the valve,a simulation of the opening process is carried out by MATLAB.Parameters are chosen based on theoretical analysis to design the test prototype of the new type of valve.Opening response time of the designed valve is tested by verifying response of the current in the coil and displacement of the main valve spool.The experimental results are in agreement with the simulated results,therefore the validity of the theoretical analysis is verified.Experimental opening response time of the valve is 48.3 ms at working pressure of 10 MPa.The flow capacity test shows that the largest effective area is 126 mm2 and the largest air flow rate is 2320 L/s.According to the result of the load driving test,the valve can meet the demands of the driving system.The proposed valve with parallel spools provides a new method for the design of a high-pressure valve with fast response and large flow rate.

Analysis of stress and natural frequencies of high-speed spatial parallel mechanism

In order to grasp the dynamic behaviors of 4-UPS-UPU high-speed spatial parallel mechanism, the stress of driving limbs and natural frequencies of parallel mechanism were investigated. Based on flexible multi-body dynamics theory, the dynamics model of 4-UPS-UPU high-speed spatial parallel mechanism without considering geometric nonlinearity was derived. The stress of driving limbs and natural frequencies of 4-UPS-UPU parallel mechanism with specific parameters were analyzed. The relationship between the basic parameters of parallel mechanism and its dynamic behaviors, such as stress of driving limbs and natural frequencies of parallel mechanism, were discussed. The numerical simulation results show that the stress and natural frequencies are relatively sensitive to the section parameters of driving limbs, the characteristic parameters of material on driving limbs, and the mass of moving platform. The researches can provide important theoretical base of the analysis of dynamic behaviors and optimal design for high-speed spatial parallel mechanism.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

Dynamic Feedforward Control of a Novel 3-PSP 3-DOF Parallel Manipulator

Parallel manipulators with less than six degrees of freedom （DOF） have been increasingly used in high-speed hybrid machine tools. The structural features of parallel manipulators are dynamic, a characteristic that is particularly significant when these manipulators are used in high-speed machine tools. However, normal kinematic control method cannot satisfy the requirements of the control system. Many researchers use model-based dynamic control methods, such as the dynamic feedforward control method. However, these methods are rarely used in hybrid machine tools because of the complex dynamic model of the parallel manipulator. In order to study the dynamic control method of parallel manipulators, the dynamic feedforward control method is used in the dynamic control system of a 3-PSP （prismatic-spherical-prismatic） 3-DOF spatial parallel manipulator used as a spindle head in a high-speed hybrid machine tool. Using kinematic analysis as basis and the Newton-Euler method, we derive the dynamic model of the parallel manipulator. Furthermore, a model-based dynamic feedforward control system consisting of both kinematic control and dynamic control subsystems is established. The dynamic control subsystem consists of two modules. One is used to eliminate the influence of the dynamic characteristics of high-speed movement, and the other is used to eliminate the dynamic disturbances in the milling process. Finally, the simulation model of the dynamic feedforward control system of the 3-PSP parallel manipulator is constructed in Matlab/Simulink. The simulations of the control system eliminating the influence of the dynamic characteristics and dynamic disturbances are conducted. A comparative study between the simulations and the normal kinematic control method is also presented.The simulations prove that the dynamic feedforward control method effectively eliminates the influence of the dynamic disturbances and dynamic characteristics of the parallel manipulator on high-speed machine tools, and significantly improves the trajectory accuracy. This is the first attempt to introduce the dynamic feedfordward control method into the 3-PSP spatial parallel manipulator whose dynamic model is complex and provides a study basis for the real-time dynamic control of the high-speed hybrid machine tools.

多线并行轨道电路电容耦合干扰机理研究

高速铁路车站并行股道多,应用场景复杂,在三线并行情况下,中间股道易受两旁线路的电磁干扰影响。当2条线路均与中间股道同向时,中间股道所受电容耦合干扰为2条线路干扰之和,且邻线耦合电容越大,干扰亦越强。为减少多线并行邻线间的电容耦合干扰,可采取改变线路相对布局、采用屏蔽等设计措施,确保高速铁路车站轨道电路工作的稳定性和可靠性。

400 km/h高铁隧道联通式缓冲结构对微气压波的影响

随着高速列车运行速度的提升,隧道口微气压波幅值剧增,强烈的爆破噪声同时影响着周边环境和附近居民的正常生活。本文研究由平行导坑与横通道组成的联通式缓冲结构对400 km/h高铁隧道微气压波的缓解作用。首先,进行400 km/h动模型试验,验证数值模拟方法的准确性;其次,基于RNG k-ε湍流模型和滑移网格技术分析联通式缓冲结构位置距隧道入口的距离D与联通式缓冲结构长度L对微气压波的影响。研究结果表明:随着D增加,微气压波的缓解率逐渐增大,在D=25 m时达到最优,微气压波幅值减少34.4%;随着L增加,微气压波幅值缓慢增加;当L=30 m时,隧道口20 m处的微气压波幅值为91 Pa,缓解率为37.1%。联通式缓冲结构与既有350 km/h高铁线路上的断面扩大开孔型缓冲结构组合,可将隧道口20 m处微气压波幅值减小至47.3 Pa,降幅达67.3%。联通式缓冲结构合理利用了修建隧道时遗留的平行导坑,可在保障施工成本几乎不变的前提下,显著缓解微气压波,保护隧道周边环境。

指控中心任务软件集中管控系统研究与关键技术

随着武器航天试验任务的增多,指控中心对任务软件快速部署、多任务并行的需求愈发迫切。设计了基于B/S架构的指控中心任务软件集中管控系统,实现了任务软件配置与监控的一体化管理;通过基于DBus与Kafka结合的数据传输机制,打通了任务软件与系统前后端数据高效交互链路;最后,重点分析了任务软件自动化部署技术、多任务并行技术、高速数据分级处理技术以及任务数据高效存储技术。

基于345-修正梯形运动规律的4-RR(SS)_(2)并联机器人运动轨迹规划

研究了一种新型四自由度高速并联机器人运动轨迹规划方法。该机器人采用单动平台结构以减轻末端平台质量,提升机器人加减速性能。建立机器人机构运动学逆解模型,通过融合345多项式和梯形运动规律的优点,构造一种可兼顾运动时长和运动平稳性的345-修正梯形运动规律。在此基础上,通过插补叠加轨迹过渡传统门形轨迹的直角部分,并统筹考虑总运动时长最短以及角加速度峰值最小为目标完成插补叠加时机的优选,最后在样机上开展运动频次试验。试验结果显示,采用优化后的运动规律和轨迹样机运动频次可提升至218次/min,工作效率较传统Adept门形轨迹提高55.7%。

Chiplet技术发展与挑战

随着半导体工艺尺寸逐渐逼近物理极限,芯片的功耗、性能和面积随工艺制程进步而带来的提升越来越小,半导体技术进入“后摩尔时代”。为进一步满足机器学习与人工智能等信息通信行业快速发展带来的高带宽通信需求,基于先进的互连和封装技术的Chiplet技术步入了我们的视野。Chiplet技术将原来的复杂多功能SoC芯片拆成多个小面积、低成本、不同工艺节点的小芯片,再进行重新组装,因其良率高、成本低、集成度高、性能强大、灵活性好、上市时间快等优点受到学术界和产业界的高度关注。本文对Chiplet的技术特征、优势、发展历史以及具体应用进行了梳理和阐述,同时详细介绍了Chiplet的关键核心技术尤其是Chiplet D2D互连技术,最后叙述了Chiplet现存的技术问题与挑战,并给出了未来发展建议。

考虑高铁平行通道分工的列车开行方案优化

结合通道内及跨区域旅客运输需求,考虑城市内部旅客出行成本,构造旅客出行服务网络,以通道内列车开行成本和旅客总出行成本最小化为目标函数,构建了基于平行通道分工的列车开行方案优化模型。以济青通道内胶济客运专线和济青高速铁路构成的平行通道为案例,验证模型的有效性。结果表明,平行通道的合理分工可以降低出行系统总成本,同时更好满足旅客出行需求。

高速通信系统中并行CRC计算及电路实现

针对高位宽数据情况下的循环冗余校验码(Cyclic Redundancy Code, CRC)电路计算工作频率较低以及资源占用过多的问题,设计并实现了一种并行CRC计算方法。该方法将CRC计算拆分为数据CRC计算和余数CRC计算两个部分,余数CRC计算由多个余数CRC计算模块级联完成,数据CRC计算模块由固定逻辑表达式实现,对二者计算结果做模二加法即得到CRC计算结果。根据数据长度选择相应的数据CRC计算模块和余数CRC计算模块的组合,以适应高位宽可变数据长度的CRC计算。以100 Gbps远程直接数据存取(Remote Direct Memory Access, RDMA)通信系统中的1 024 bits数据位宽CRC-32的计算为例,在VCU118开发板上实现了该算法的硬件电路。实验结果表明,所提设计仅使用4 760个查找表和2 658个触发器,整个系统带宽最高可达97.85 Gbps,最高工作频率可达326 MHz。与其他相关方法相比,提出的方法具有较高的工作频率且资源占用较少。

A scheme of optical interconnection for super high speed parallel computer

An optical cross connection network which adopts coarse wavelength division multiplexing (CWDM) and data packet is introduced. It can be used to realize communication between multi-CPU and multi-MEM in parallel computing system. It provides an effective way to upgrade the capability of parallel computer by combining optical wavelength division multiplexing (WDM) and data packet switching technology. CWDM used in network construction, optical cross connection (OXC) based on optical switch arrays, and data packet format used in network construction were analyzed. We have also done the optimizing analysis of the number of optical switches needed in different scales of network in this paper. The architecture of the optical interconnection for 8 wavelength channels and 128 bits parallel transmission has been researched. Finally, a parallel transmission system with 4 nodes, 8 channels per node, has been designed.

Evaluation of the power consumption of a high-speed parallel robot

An inverse dynamic model of a high-speed parallel robot is established based on the virtual work principle. With this dynamic model, a new evaluation method is proposed to measure the power consumption of the robot during pick-and-place tasks. The power vector is extended in this method and used to represent the collinear velocity and acceleration of the moving platform. After- ward, several dynamic performance indices, which are homogenous and possess obvious physical meanings, are proposed. These indices can evaluate the power input and output transmissibility of the robot in a workspace. The distributions of the power input and output transmissibility of the high-speed parallel robot are derived with these indices and clearly illustrated in atlases. Furtherly, a low- power-consumption workspace is selected for the robot.

A Parallel Actuated Pantograph Leg for High-speed Locomotion

High-speed running is one of the most important topics in the field of legged robots which requires strict constraints on structural design and control. To solve the problems of high acceleration, high energy consumption, high pace frequency and ground impact during high-speed movement, this paper presents a parallel actuated pantograph leg with an approximately decoupled configuration. The articulated leg features in light weight, high load capacity, high mechanical efficiency and structural stability. The similarity features of force and position between the control point and the foot are analyzed. The key design parameters, K1 and K2, which concern the dynamic performances, are carefully optimized by comprehensive evaluation of the leg inertia and mass within the maximum foot trajectory, A control strategy that incorporates virtual Spring Loaded Inverted Pendulum （SLIP） model and active force is also proposed to test the design. The strategy can implement highly flexible impedance without mechanical springs, which substantially simplifies the design and satisfies the variable stiffness requirements during high-speed running. The rationality of the structure and the effectiveness of the control law are validated by simulation and experiments.

昌九高铁扬子洲赣江公铁合建连续钢桁梁桥设计研究

昌九高铁为时速350 km的高速铁路,其南昌扬子洲跨赣江中支主桥根据通航、防洪要求跨度采用(78+134+152+134+78) m,该桥为国内首座高速铁路公铁混层合建的大跨径平行弦连续钢桁梁桥,同时该主梁为首座采用带双层挑臂的钢桁梁断面。为掌握该类型桥梁的关键技术及总结该类型桥的设计经验,开展系列研究,运用数值分析的方法,进行结构静动力分析及车桥耦合分析。结果表明:(1)带双层挑臂的钢桁梁断面具有剪力滞效应小、结构整体性强、跨越能力大、腹杆及横梁受力小、行车视野好及造价经济等优点,带双层挑臂的钢桁梁断面为公铁合建桥的适宜断面形式;(2)带双层挑臂的钢桁梁桥,墩顶处上层桥面系、跨中处上层桥面系及跨中处下层桥面系,其轴力主要由桥面板承担,分别占比为61.4%、68.7%及60.0%,墩顶处下层桥面系轴力主要由下弦杆承担,占比为72.5%;(3)带双层挑臂的钢桁梁剪力滞系数为墩顶上桥面(1.49)>跨中下桥面(1.38)>跨中上桥面(1.13);(4)带双层挑臂的平行弦连续钢桁梁桥能满足时速350 km公铁合建桥的行车运行要求,结构静动力性能良好,适用跨径能达150 m及以上。

一种航空发动机进气畸变试验测试系统研究

航空发动机的进气畸变试验对其稳定性具有重要的意义。为了满足航空发动机进气畸变发生器测试系统的需求,提出了一种基于3D打印技术和高速多通道数据采集的测试系统设计方法,在保证数据准确的前提下,提高了系统设计的效率,完成了数据的高速实时采集。在此基础上,采用时空滤波和流体场重构的方法对数据进行处理,并基于MATLAB完成了测试系统界面的设计。最后,分别进行了测压耙校准试验和3种畸变图谱的风洞试验。试验结果表明,测试通道与风洞出口总压值小于0.2 kPa,畸变图谱的测试畸变指数与目标畸变指数误差小于1.2%,验证了所采用的数据处理算法和测试系统的有效性和准确性。

应用于红外大面阵数据传输的接口电路设计

红外大面阵(2560×2048)数字读出电路对芯片数据接口有高速、低功耗、强驱动能力的需求。采用0.18μm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺设计了4∶1并串转换电路、电平转换电路以及采用预加重技术的低压差分信号(Low Voltage Differential Signal,LVDS)驱动器电路。并串转换电路采用双沿采样的树形结构降低时钟频率,电平转换电路采用正反馈结构提升速度,LVDS驱动电路采用可编程电流大小的预加重副通路对主通路进行高频分量补偿,以保证驱动能力和提升高速信号的完整性。接口的数据传输速率可达到1 Gbit/s。当负载电容为2 pF时,一个通道的功耗为15.8 mW@1 Gbit/s;当负载电容为8 pF且打开预加重时,一个通道的功耗为19 mW@1Gbit/s,输出电压摆幅为350 mV,输出共模电平为1.21 V,LVDS驱动电路的所有参数均满足标准协议。