Field Programmable Gate Array(FPGA),combined with ARM(Advanced RISC Machines) is increasingly employed in the portable data acquisition(DAQ) system for nuclear experiments to reduce the system volume and achieve power...Field Programmable Gate Array(FPGA),combined with ARM(Advanced RISC Machines) is increasingly employed in the portable data acquisition(DAQ) system for nuclear experiments to reduce the system volume and achieve powerful and multifunctional capacity.High-speed data transmission between FPGA and ARM is one of the most challenging issues for system implementation.In this paper,we propose a method to realize the high-speed data transmission by using the FPGA to acquire massive data from FEE(Front-end electronics) and send it to the ARM whilst the ARM to transmit the data to the remote computer through the TCP/IP protocol for later process.This paper mainly introduces the interface design of the high-speed transmission method between the FPGA and the ARM,the transmission logic of the FPGA,and the program design of the ARM.The theoretical research shows that the maximal transmission speed between the FPGA and the ARM through this way can reach 50 MB/s.In a realistic nuclear physics experiment,this portable DAQ system achieved 2.2 MB/s data acquisition speed.展开更多
研究基于有线通信的高速数据传输技术,旨在优化数据传输过程,提高数据的传输速率和可靠性。采用基于流控制和拥塞控制的传输控制协议(Transmission Control Protocol,TCP)优化算法,在确保通信网络稳定性的同时,提高数据传输性能。将该...研究基于有线通信的高速数据传输技术,旨在优化数据传输过程,提高数据的传输速率和可靠性。采用基于流控制和拥塞控制的传输控制协议(Transmission Control Protocol,TCP)优化算法,在确保通信网络稳定性的同时,提高数据传输性能。将该技术应用于输电网的视频实时监控,并对传输速率和可靠性进行评估。实验结果显示,该方法在输电网视频实时监控中实现了高效、稳定的数据传输。展开更多
高速服务器主板主芯片到存储器的高速信号传输通过Double Data Rate(简称DDR)技术实现,传输高速信号的连接线简称为DDR阻抗线。因主芯片相对存储器位置能布设管脚的空间要小,从主芯片到存储器的DDR高速阻抗线呈扇出形状,主芯片位置的阻...高速服务器主板主芯片到存储器的高速信号传输通过Double Data Rate(简称DDR)技术实现,传输高速信号的连接线简称为DDR阻抗线。因主芯片相对存储器位置能布设管脚的空间要小,从主芯片到存储器的DDR高速阻抗线呈扇出形状,主芯片位置的阻抗线线宽相对存储器位置要小,存在阻抗不连续问题。对靠近主芯片位置的DDR阻抗线增加规则的凸耳状走线可提升整段DDR阻抗不匹配问题。增加规则的凸耳走线的阻抗线又称Tabbed Routiing阻抗(简称TAB阻抗)。探究布设不同形状和不同尺寸的TAB设计来提升阻抗不连续问题,根据材料等级选择一种最佳的布线设计模式,对TAB阻抗设计及生产制作控制都有较大指导意义。展开更多
文摘Field Programmable Gate Array(FPGA),combined with ARM(Advanced RISC Machines) is increasingly employed in the portable data acquisition(DAQ) system for nuclear experiments to reduce the system volume and achieve powerful and multifunctional capacity.High-speed data transmission between FPGA and ARM is one of the most challenging issues for system implementation.In this paper,we propose a method to realize the high-speed data transmission by using the FPGA to acquire massive data from FEE(Front-end electronics) and send it to the ARM whilst the ARM to transmit the data to the remote computer through the TCP/IP protocol for later process.This paper mainly introduces the interface design of the high-speed transmission method between the FPGA and the ARM,the transmission logic of the FPGA,and the program design of the ARM.The theoretical research shows that the maximal transmission speed between the FPGA and the ARM through this way can reach 50 MB/s.In a realistic nuclear physics experiment,this portable DAQ system achieved 2.2 MB/s data acquisition speed.
文摘研究基于有线通信的高速数据传输技术,旨在优化数据传输过程,提高数据的传输速率和可靠性。采用基于流控制和拥塞控制的传输控制协议(Transmission Control Protocol,TCP)优化算法,在确保通信网络稳定性的同时,提高数据传输性能。将该技术应用于输电网的视频实时监控,并对传输速率和可靠性进行评估。实验结果显示,该方法在输电网视频实时监控中实现了高效、稳定的数据传输。
文摘高速服务器主板主芯片到存储器的高速信号传输通过Double Data Rate(简称DDR)技术实现,传输高速信号的连接线简称为DDR阻抗线。因主芯片相对存储器位置能布设管脚的空间要小,从主芯片到存储器的DDR高速阻抗线呈扇出形状,主芯片位置的阻抗线线宽相对存储器位置要小,存在阻抗不连续问题。对靠近主芯片位置的DDR阻抗线增加规则的凸耳状走线可提升整段DDR阻抗不匹配问题。增加规则的凸耳走线的阻抗线又称Tabbed Routiing阻抗(简称TAB阻抗)。探究布设不同形状和不同尺寸的TAB设计来提升阻抗不连续问题,根据材料等级选择一种最佳的布线设计模式,对TAB阻抗设计及生产制作控制都有较大指导意义。
