High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.

Breakdown Voltage and Charge to Breakdown Investigation of Gate Oxide of 0.18μm Dual Gate CMOS Process with Different Measurement Methods

Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate oxide of a 0.18μm dual gate CMOS process. Voltage ramps （V-ramp） and current ramps （J-ramp） are used to evaluate gate oxide reliability. The thin and thick gate oxides are all evaluated in the accumulation condition. Our experimental results show that the measurement methods affect Vbd only slightly but affect Qbd seriously,as do the measurement conditions.This affects the I-t curves obtained with the J-ramp and V-ramp methods. From the I-t curve,it can be seen that Qbd obtained using a J-ramp is much bigger than that with a V-ramp. At the same time, the Weibull slopes of Qbd are definitely smaller than those of Vbd. This means that Vbd is more reliable than Qbd, Thus we should be careful to use Qbd to evaluate the reliability of 0.18μm or beyond CMOS process gate oxide.

Analysis of hot-carrier degradation in N-LDMOS transistor with step gate oxide

In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Compared with the conventional configuration, the electric field under the gate along the Si-SiO2 interface in the presented N-LDMOS can be greatly reduced, which favors reducing the hot-carrier degradation. The step gate oxide can be achieved by double gate oxide growth, which is commonly used in some smart power ICs. The differences in hot-carrier degradations between the novel structure and the conventional structure are investigated and analyzed by 2D technology computer-aided design（TCAD）numerical simulations, and the optimal length of the thick gate oxide part in the novel N-LDMOS device can also be acquired on the basis of maintaining the characteristic parameters of the conventional device. Finally, the practical degradation measurements of some characteristic parameters can also be carried out. It is found that the hot-carrier degradation of the novel N-LDMOS device can be improved greatly.

SILC Mechanism in Degraded Gate Oxide of Different Thickness

It is shown that traps are generated asymmetrically in the thin gate oxides with different thickness during high field degradation,as well as the multi-mechanism plays role in the Stress Induced Leakage Current (SILC).These factors perform differently in gate oxide of different thickness.A comparison is drew between several analyzing models.Trap assisted tunneling is preferred for thinner samples,while Pool-Frankel like mechanism or thermal emission mechanism should apply to the thick ones.

New Forward Gated-Diode Technique for Separating Front Gate Interface- from Oxide-Traps Induced by Hot-Carrier-Stress in SOI-NMOSFETs

The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.

Substrate Hot Holes Injection Induced Breakdown Characteristics of Thin Gate Oxides

A substrate hot holes injection method is used to quantitatively examine the roles of electrons and holes separately in thin gate oxides breakdown.The shift of threshold voltage under different stress is discussed.It is indicated that positive charges are trapped in SiO 2 while hot electrons are necessary for SiO 2 breakdown.The anode holes injection model and the electron traps generation model is linked into a consistent model,describing the oxide wearout as an electron correlated holes trap creation process.The results show that the limiting factor in thin gate oxides breakdown depends on the balance between the amount of injected hot electrons and holes.The gate oxides breakdown is a two step process.The first step is hot electron's breaking Si-O bonds and producing some dangling bonds to be holes traps.Then the holes are trapped and a conducted path is produced in the oxides.The joint effect of hot electrons and holes makes the thin gate oxides breakdown complete.

Effect of Metal Contamination on Characteristics of Ultra-Thin Gate Oxide

The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments are carried out by depositing a few ppm contaminated metal and low pH solutions on the wafers.The maximum metal surface concentration is controlled at about 10 12 cm -2 level in order to simulate metal contamination during ultra clean processing.A ramped current stress for intrinsic charge to breakdown measurements with gate injection mode is used to examine the characteristics of these ultra thin gate oxides and the effect of metal contamination on GOI.It is the first time to investigate the influence of metal Zr and Ta contamination on 2 5nm ultra thin gate oxide.It is demonstrated that there is little effect of Al contamination on GOI,while Zr contamination is the most detrimental to GOI,and early breakdown has happened to wafers contaminated by Ta.

Scaling effects of single-event gate rupture in thin oxides

The dynamics of the excess carriers generated by incident heavy ions are considered in both SiO2 and Si substrate. Influences of the initial radius of the charge track, surface potential decrease, external electric field, and the LET value of the incident ion on internal electric field buildup are analyzed separately. Considering the mechanisms of recombination, impact ionization, and bandgap tunneling, models are verified by using published experimental data. Moreover, the scaling effects of single-event gate rupture in thin gate oxides are studied, with the feature size of the MOS device down to 90 nm. The walue of the total electric field decreases rapidly along with the decrease of oxide thickness in the first period （1 2 nm to 3.3 nm）, and then increases a little when the gate oxide becomes thinner and thinner （3.3 nm to 1.8 nm）.

Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.

Novel Oxide Trap Behavior in Ultra Thin Gate and Its Study by PDO Method

The degradation of MOSFETs under high field stress has been investigated for a l ong time. The degradation is due to the newly generated traps. As the gate thick ness scaled down rapidly, a conventional method for detecting oxide traps, such as C-V or subthreshold swing, is no longer effective. Some new phenome na a lso appear, such as Stress Induced Leakage Current (SILC) and soft-breakdown. T he oxide traps’ behavior and their characteristics are the key problems in the s tudy of degradation. By extracting the change of transition coefficients from th e I-V curve and using the PDO (Proportional Differential Operator) meth od, various oxide traps can be distinguished and as would be helpful in the dete rmination of trap behavior changes during the degradation process.

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10^(18) cm^(-3) and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.

Gate leakage current of NMOSFET with ultra-thin gate oxide

As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.

A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop （TFS） superjunction （S J） insulated gate bipolar transistor （IGBT） with a buried oxide （BO） layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT （Conv-SJ）, the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop （gce（on）） and an improved tradeoff between gee（on） and turn-off loss （Eoff）, with no breakdown voltage （BV） degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5μm and Nn = Np = 3 × 10^15 cm^-3, the Vce（on） and Eoff of the proposed structure are 1.08 V and 2.81 mJ/cm2 with the collector doping concentration Nc = 1 × 10^18 cm^-3 and 1.12 V and 1.73 mJ/cm2 with Nc = 5 × 10^17 cm^-3, respectively. However, with the same device parameters, the Vce（on） and Eoff for the Conv-SJ are 1.81 V and 2.88 mJ/cm2 with Nc= 1 × 10^18 cm^-3 and 1.98 V and 2.82 mJ/cm2 with Nc = 5 ×10^17 cm^-3, respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.

Equivalent oxide thickness scaling of Al_2O_3/Ge metal-oxide-semiconductor capacitors with ozone post oxidation

Aluminum-oxide films deposited as gate dielectrics on germanium （Ge） by atomic layer deposition were post oxidized in an ozone atmosphere. No additional interfacial layer was electron microscopy and X-ray photoelectron spectroscopy detected by the high-resolution cross-sectional transmission measurements made after the ozone post oxidation （OPO） treatment. Decreases in the equivalent oxide thickness of the OPO-treated Al2O3/Ge MOS capacitors were confirmed. Furthermore, a continuous decrease in the gate leakage current was achieved with increasing OPO treatment time. The results can be attributed to the film quality having been improved by the OPO treatment.

Current Progress of Hf(Zr)-Based High-k Gate Dielectric Thin Films

With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.

Novel attributes and design considerations of effective oxide thickness in nano DG MOSFETs

Impacts of effective oxide thickness on a symmetric double-gate MOSFET with 9-nm gate length are studied, using full quantum simulation. The simulations are based on a self-consistent solution of the two-dimensional （2D） Poisson equation and the Schr6dinger equation within the non-equilibrium Green＇s function formalism. Oxide thickness and gate dielectric are investigated in terms of drain current, on-off current ratio, off current, sub-threshold swing, drain induced barrier lowering, transconductance, drain conductance, and voltage. Simulation results illustrate that we can improve the device performance by proper selection of the effective oxide thickness.