High-Speed,Robust CMOS Dynamic Circuit Design

A novel circuit with a narrow pulse driving structure is proposed for enhancing the noise immunity and improving the performance of wide fan-in dynamic circuits. Also,an analytical mode that agrees well with simulations is presented for transistor sizing. Simulation results show that an improvement of up to 12% over the conventional technique at 1GHz is obtained with this circuit,which can run 1.6 times faster than the existing technique with the same noise immunity.

AN ANALYSIS METHOD FOR HIGH-SPEED CIRCUIT SYSTEMS

A new method for analyzing high-speed circuit systems is presented. The method adds transmission line end currents to the circuit variables of the classical modified nodal approach. Then the matrix equation describing high-speed circuit system can be formulated directly and analyzed conveniently for its normative form. A time-domain analysis method for transmission lines is also introduced. The two methods are combined together to efficiently analyze high-speed circuit systems having general transmission lines. Numerical experiment is presented and the results are compared with that calculated by Hspice.

Power supply arm protection scheme of high-speed railway based on wide-area current differential

When fault occurs on cross-coupling autotransformer(AT)power supply traction network,the up-line and down-line feeder circuit breakers in the traction substation trip at the same time without selectivity,which leads to an extended power failure.Based on equivalent circuit and Kirchhoff’s current law,the feeder current characteristic in the substation,AT station and sectioning post when T-R fault,F-R fault,and T-F fault occur are analyzed and their expressions are obtained.When the traction power supply system is equipped with wide-area protection measurement and control system,the feeder protection device in each station collects the feeder currents in other two stations through the wide-area protection channel and a wide-area current differential protection scheme based on the feeder current characteristic is proposed.When a short-circuit fault occurs in the power supply arm,all the feeder protection devices in each station receive the feeder currents with time stamp in other two stations.After data synchronous processing and logic judgment,the fault line of the power supply arm can be identified and isolated quickly.The simulation result based on MATLAB/Simulink shows that the power supply arm protection scheme based on wide-area current differential has good fault discrimination ability under different fault positions,transition resistances,and fault types.The verification of measured data shows that the novel protection scheme will not be affected by the special working conditions of the electrical multiple unit(EMU),and reliability,selectivity,and rapidity of relay protection are all improved.

Electromagnetic Analysis and Optimization of High-speed Maglev Linear Synchronous Motor Based on Field-circuit Coupling

High speed maglev train has become a new non-contact transportation mode mainly studied in recent years because of its non-sticking and high speed characteristics.Firstly,the finite element model of the long stator linear synchronous motor(LSM)is established based on the structure of the test prototype.After calculation,it is compared with the experimental data and verified.On this basis,a field-circuit coupling model based on inverter circuit is established,and the influence of carrier wave ratio change on the output characteristics of LSM is calculated and analyzed.Finally,the filter circuit is introduced into the field-circuit coupling model,and the influence of the filter circuit on the output characteristics of the LSM is compared and analyzed.

Sensitivity analysis of distributed parameter elements in high-speed circuit networks

This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calculated from electrical and physical parameters of the distributed parameter elements. The proposed method is a direct numerical method of time-space discretization and does not require complicated mathematical deductive process. Therefore, it is very convenient to program this method. It can be applied to sensitivity analysis of general transmission lines in linear or nonlinear circuit networks. The proposed method is second-order-accurate. Numerical experiment is presented to demonstrate its accuracy and efficiency.

Analysis of Temperature Rise in High-Speed Permanent Magnet Synchronous Traction Motors by Coupling the Equivalent Thermal Circuit Method and Computational Fluid Dynamics

To solve the problem of temperature rise caused by the high power density of high-speed permanent magnet synchronous traction motors,the temperature rise of various components in the motor is analyzed by coupling the equivalent thermal circuit method and computational fluid dynamics.Also,a cooling strategy is proposed to solve the problem of temperature rise,which is expected to prolong the service life of these devices.First,the theoretical bases of the approaches used to study heat transfer and fluid mechanics are discussed,then the fluid flow for the considered motor is analyzed,and the equivalent thermal circuit method is introduced for the calculation of the temperature rise.Finally,the stator,rotor loss,motor temperature rise,and the proposed cooling method are also explored through experiments.According to the results,the stator temperature at 50,000 r/min and 60,000 r/min at no-load operation is 68℃ and 76℃,respectively.By monitoring the temperature of the air outlets inside and outside the motor at different speeds,it is also found that the motor reaches a stable temperature rise after 65 min of operation.Coupling of the thermal circuit method and computational fluid dynamics is a strategy that can provide the average temperature rise of each component and can also comprehensively calculate the temperature of each local point.We conclude that a hybrid cooling strategy based on axial air cooling of the inner air duct of the motor and water cooling of the stator can meet the design requirements for the ventilation and cooling of this type of motors.

Minimizing crosstalk for high-speed and high-density bus systems using the sample-decision method

This paper presents a method based on a sample-decision(SD) circuit to suppress crosstalk and noise for a high-speed and high-density bus system.A method to count the number of times of SD for different length of transmission lines is presented and a bit error rates(BERs) formula is given by the SD circuit.It is shown that for long transmission line systems,multiple SD circuits can improve the BERs significantly.Circuits simulation for single SD method is also done,it is found that when the amplitude peak values of the superposed crosstalk and noise are less than half of the corresponding signal ones,they will be eliminated completely for the cases investigated.

New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits

New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

Design of a Low-Power CMOS LVDS I/O Interface Circuit

The paper presents the design and implementation of LVDS （low-voltage differential signaling） receiver circuit, fully compatible with LVDS standard. The proposed circuit is composed of the telescopic amplifier and the comparator with internal hysteresis. The receiver supports 3.5 Gbps data rate with 7.4 mA current at 1.8 V supply according to post-layout circuit simulations. The circuit has the power consumption of 13.1 MW. Comparing with the conventional circuit, the circuit is achieved to reduce the power consumption by 19.1% and the data rate by 14.3 %. The validity and effectiveness of the proposed circuit are verified through the circuit simulation with Samsung 0.18 μm CMOS （complementary metal-oxide-semiconductor） standard technology under the 1.8 V supply voltage.

Interruption Characteristics of High-speed Switches in 500 kV Fault Current Limiter with High Coupled Split Reactance

A 500 kV high-voltage AC fault current limiter(FCL)based on a high coupled split reactor(HCSR)is pro-posed by the National key R&D project team.Low impedance under normal conditions and high impedance under short-circuit conditions are accomplished by the cooperation of HCSR and high-speed switches.High-speed switches play an important role in current limiting processes,thus interruption characteristics of the high-speed switch in the 500 kV FCL are studied in this paper.The simulation model of the FCL and the external equivalent power grid are established.The short-circuit current and recovery voltage characteristics of the high-speed switch in FCL are simulated.The results show that maximum DC component of the short-circuit current of the high-speed switch reaches 91%,the maximum peak value is 118 kA,and the longest arcing time is 14.8 ms.There is a discontinuity in the curve of the short-circuit current peak and arcing time as a function of the short-circuit occurrence time;the peak recovery voltage of a single break of the high-speed switch has a maximum value of 87.5 kV under a three-phase ungrounded short-circuit condition,and the rate of rise of recovery voltage is o.22 kV/s.The recovery voltage peak shows a period change with the short-circuit occurrence time,and the period is 10 ms.The effects of the shunt capacitor value and short-circuit ground resistance on the recovery voltage of high-speed switching are also studied.The research can be used for reference by R&D personnel and testersof500kVFCLs.Index Terms-Fault current limiter(FCL),high coupled split reactor(HCSR),high-speed switch,interruption characteristics,short circuit current.

Gigahertz-rate-switchable wavefront shaping through integration of metasurfaces with photonic integrated circuit

Achieving spatiotemporal control of light at high speeds presents immense possibilities for various applications in communication,computation,metrology,and sensing.The integration of subwavelength metasurfaces and optical waveguides offers a promising approach to manipulate light across multiple degrees of freedom at high speed in compact photonic integrated circuit(PIC)devices.Here,we demonstrate a gigahertz-rate-switchable wavefront shaping by integrating metasurface,lithium niobate on insulator photonic waveguides,and electrodes within a PIC device.As proofs of concept,we showcase the generation of a focus beam with reconfigurable arbitrary polarizations,switchable focusing with lateral focal positions and focal length,orbital angular momentum light beams as well as Bessel beams.Our measurements indicate modulation speeds of up to the gigahertz rate.This integrated platform offers a versatile and efficient means of controlling the light field at high speed within a compact system,paving the way for potential applications in optical communication,computation,sensing,and imaging.

阻塞斩波三相交交变频电源的FPGA控制实现

变频技术是重要的节能技术,所以针对低频或转速不恒定的节能设备,提出了基于FPGA数字控制的三相交交直接变频电源技术。用VHDL语言对主控芯片FPGA编写程序,其输出的高频SPWM信号经驱动电路后作为电源和负载间开关MOSFET的控制信号。MOSFET周期性地部分阻塞电源不能达到负载来改变输出电压的频率,同时在放行的时区斩波来改变输出电压的幅值。基于Matlab仿真平台,对系统进行了建模和仿真,仿真结果验证了该技术的正确性。最后给出了频率为7.14 Hz和2.63 Hz的实验波形,实验结果证明了该技术的可行性。

闪光有效光强的测试方法研究

有效光强是闪光光源特性的基本评价参数,是研制闪光光源的重要依据。主要介绍了闪光光源有效光强的测试原理及其测试装置,通过对闪光光源有效光强测量中现存问题的分析,提出了相应的解决方法,并对测试仪器研制中的关键技术包括同步控制技术、标准探测器、高速数据采集电路等内容进行了讨论,这些技术已成功的运用于自行研制的闪光有效光强测试仪。

20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS

A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET logic structure latch, its power supply voltage is lower and the speed is faster. In addition, the negative feedback is used in the buffer circuit to widen its bandwidth. Measurement results show that the chip can work at the data rate of 20Gb/ s. The supply voltage is 1.8V and the current,including the buffer circuit, is 72mA.

Design and implementation of high-speed real-time data acquisition system based on FPGA

The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.

Design of 4.25 Gbps Small Form-factor Pluggable(SFP) Transceiver

Compact, hot-pluggable, and data-agnostic, SFP modules bring up to 4.25 Gbps to a flexible new form factor. The SFP transceiver which is the core device of optical communication is always the research focus in the field of optical communication for both telecommunication and data communication applications. The working principles of SFP including the transmitter components, the receiver components and the microcontroller are discussed in detail. The basic theory of high-speed signal and the concept of high - speed circuit, high-speed board design techniques are presented. A new design of high performance, cost effective SFP transceiver and PCB layout are also presented. The performance of the transceiver is analyzed and the characteristics of the sample are coincident with the expected ones. The status of the transceiver can be monitored and controlled by F C bus through the interface in real time. This transceiver can meet the requirement of SFF-8472.

A novel SRAM test method based on embeddedimplementation on FPGA

With the development of satellite based remote sensors, embedded systems become moreand more popular in space camera electronics. Static Random Access Memory（SRAM） is one kind of themost widely used memories due to its merits of high efficiency and low power dissipation, but testing itsfunction still depends on writing testing modules with hardware description language, which results in lowdeveloping efficiency and low reliability. In this paper, an embedded testing method is proposed, which isbased on MicroBlaze and its speed increasing function design. Implementation of the test method is basedon reusable Intellectual Property（IP） technique and greatly improves data transfer speed. With this method,secondary development of SRAM test system can be made in application layer instead of fundamentallogical layer, which simplifies the system design. It is not only more efficient and more reliable, but alsoeasier to transplant, which greatly reduces test design cost. The validity and feasibility of the method havebeen proved by test results.

Computer Program Calculation for Distortion of Wide-Band Track and Hold Amplifier

Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method. The other calculates the weekly nonlinear distortion by using a Volterra series method and a nodal formulation. Comparative calculation results for the diode bridge THA have shown good agreement with these two computer program calculation methods, whereas the overall computational efficiency of the nonlinear-current method is better than that of the nodal formulation method in a special evaluation.

Optimization design of a full asynchronous pipeline circuit based on null convention logic

This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline.Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode.The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules.Performance penalty brought by null cycle is reduced while the data processing capacity is increased.The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS technology.Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption.This indicates the new design proposal is preferable for high-speed as ynchronous designs due to its high throughput and delay-insensitivity.

Switching circuits based on comparison operations and multiple-β transistor

By using comparison operations, three basic operations, AND, OR and NOT, in Boolean algebra are re-defined Based on the characteristic that the voltage signals are easy to implement comparison operation, various logic functions realized by connecting emitters of the bipolar transistor are analyzed. Furthermore, a novel multiple-β transistor and the linear AND-OR gate, which is composed of the transistor, are investigated. Super high-speed characteristic and multiple-cascade capability of the linear AND-OR gate are verified by PSPICE simulation. Based on the analysis of high-speed switch, which is compatible with the linear AND-OR gate, a high-speed inverter is proposed, which is composed of multiple-β transistors. The corresponding flip-flop design is also given. Finally, the criterion for using linear AND-OR gate to design high-speed switching circuits are presented. Some combinational and sequential circuits are designed as the practical examples. Discussion indicates that the switching circuits based on multiple-β transistor can be applied in high-speed design field.