Graphene field-effect transistors(GFET) have attracted much attention in the radio frequency(RF) and microwave fields because of its extremely high carrier mobility. In this paper, a GFET with a gate length of 5 μm i...Graphene field-effect transistors(GFET) have attracted much attention in the radio frequency(RF) and microwave fields because of its extremely high carrier mobility. In this paper, a GFET with a gate length of 5 μm is fabricated through the van der Walls(vdW) transfer process, and then the existing large-signal GFET model is described, and the model is implemented in Verilog-A for analysis in RF and microwave circuits. Next a double-balanced mixer based on four GFETs is designed and analyzed in advanced design system(ADS) tools. Finally, the simulation results show that with the input of 300 and 280 MHz,the IIP3 of the mixed signal is 24.5 dBm.展开更多
A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS pro...A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.展开更多
The design and analysis of a reconfigurable dual-band down-conversion mixer for IMT-advanced （3.4 3.6 GHz） and UWB （4.2-4.8 GHz） applications are presented. Based on a folded double-balanced Gilbert cell, which is...The design and analysis of a reconfigurable dual-band down-conversion mixer for IMT-advanced （3.4 3.6 GHz） and UWB （4.2-4.8 GHz） applications are presented. Based on a folded double-balanced Gilbert cell, which is well known for its low voltage, simplicity and well balanced performance, the mixer adopts a capacitive cross-coupling technique for input matching and performance improvement. Switched capacitors and resistors are added to shift the working bands. Fabricated in a TSMC 0.13 #m process, the test results show flat conversion gains from 9.6 to 10.3 dB on the IMT-A band and from 9.7 to 10.4 dB on the UWB band, with a noise figure of about 15 dB on both bands. The input third-order intercept points （lIP3） are about 7,3 dBm on both of the frequency bands. The whole chip consumes 11 mW under 1.2 V supply and the total area of the layout is 0.76 × 0.65 mm^2.展开更多
A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To ...A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To optimize noise as well as linearity,a differential common-source LNA with capacitive cross- coupling is used,which only consumes current of 1.8 mA from a 1.2 V power supply.Following LNA,a two-stage current-steering VGA is adopted for gain tuning.To extend the overall bandwidth,a three-stage staggered peaking technique is used.Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6-7 GHz,a minimum noise figure of 4.5 dB and a largest IIP_3 of-11 dBm.The core receiver (without test buffer) consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm^2 area.展开更多
Using a Volterra series, an explicit formula is derived for the connection between input 3rd-order intercept point and collector bias current （IcQ） in a common-emitter bipolar junction transistor amplifier. The anal...Using a Volterra series, an explicit formula is derived for the connection between input 3rd-order intercept point and collector bias current （IcQ） in a common-emitter bipolar junction transistor amplifier. The analysis indicates that the larger/CQ is, the more linear the amplifier is. Furthermore, this has been verified by experiment. This study also integrates a method called dynamic bias current for expanding the dynamic range of an LNA （low noise amplifier） as an application of the analysis result obtained above. IMR3 （3rd-order intermodulation rate） is applied to evaluate the LNA＇s performance with and without adopting this method in this study.展开更多
基金National Natural Science Foundation of China(Grant Nos.51925208,61974157,61851401,62122082)Key Research Project of Frontier Science,Chinese Academy of Sciences(QYZDB-SSW-JSC021)+3 种基金Strategic Priority Research Program(B)of the Chinese Academy of Sciences(XDB30030000)National Science and Technology Major Project(2016ZX02301003)Science and Technology Innovation Action Plan of Shanghai Science and Technology Committee(20501130700)Science and Technology Commission of Shanghai Municipality(19JC1415500)。
文摘Graphene field-effect transistors(GFET) have attracted much attention in the radio frequency(RF) and microwave fields because of its extremely high carrier mobility. In this paper, a GFET with a gate length of 5 μm is fabricated through the van der Walls(vdW) transfer process, and then the existing large-signal GFET model is described, and the model is implemented in Verilog-A for analysis in RF and microwave circuits. Next a double-balanced mixer based on four GFETs is designed and analyzed in advanced design system(ADS) tools. Finally, the simulation results show that with the input of 300 and 280 MHz,the IIP3 of the mixed signal is 24.5 dBm.
文摘A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.
基金supported by the National Science and Technology Major Special Project(No.2012ZX03001-019)
文摘The design and analysis of a reconfigurable dual-band down-conversion mixer for IMT-advanced （3.4 3.6 GHz） and UWB （4.2-4.8 GHz） applications are presented. Based on a folded double-balanced Gilbert cell, which is well known for its low voltage, simplicity and well balanced performance, the mixer adopts a capacitive cross-coupling technique for input matching and performance improvement. Switched capacitors and resistors are added to shift the working bands. Fabricated in a TSMC 0.13 #m process, the test results show flat conversion gains from 9.6 to 10.3 dB on the IMT-A band and from 9.7 to 10.4 dB on the UWB band, with a noise figure of about 15 dB on both bands. The input third-order intercept points （lIP3） are about 7,3 dBm on both of the frequency bands. The whole chip consumes 11 mW under 1.2 V supply and the total area of the layout is 0.76 × 0.65 mm^2.
基金supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University.
文摘A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To optimize noise as well as linearity,a differential common-source LNA with capacitive cross- coupling is used,which only consumes current of 1.8 mA from a 1.2 V power supply.Following LNA,a two-stage current-steering VGA is adopted for gain tuning.To extend the overall bandwidth,a three-stage staggered peaking technique is used.Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6-7 GHz,a minimum noise figure of 4.5 dB and a largest IIP_3 of-11 dBm.The core receiver (without test buffer) consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm^2 area.
基金Project supported by the Tianjin Natural Science Foundation,China(No.09JCYBJC00700)
文摘Using a Volterra series, an explicit formula is derived for the connection between input 3rd-order intercept point and collector bias current （IcQ） in a common-emitter bipolar junction transistor amplifier. The analysis indicates that the larger/CQ is, the more linear the amplifier is. Furthermore, this has been verified by experiment. This study also integrates a method called dynamic bias current for expanding the dynamic range of an LNA （low noise amplifier） as an application of the analysis result obtained above. IMR3 （3rd-order intermodulation rate） is applied to evaluate the LNA＇s performance with and without adopting this method in this study.
