An RF frontend circuit design of a Compass and GPS dual-mode dual-channel image rejection radio receiver

This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μm TSMC CMOS process.Except for a few passive components for input matching,other components such as an off-chip low noise amplifier or a balun are not required.With a non-tunable passive image rejection filter,the receiver frontend can achieve around 60 dB gain and 34 dB image rejection.

Iterative static modeling of channelized reservoirs using history-matched facies probability data and rejection of training image

Most inverse reservoir modeling techniques require many forward simulations, and the posterior models cannot preserve geological features of prior models. This study proposes an iterative static modeling approach that utilizes dynamic data for rejecting an unsuitable training image(TI) among a set of TI candidates and for synthesizing history-matched pseudo-soft data. The proposed method is applied to two cases of channelized reservoirs, which have uncertainty in channel geometry such as direction, amplitude, and width. Distance-based clustering is applied to the initial models in total to select the qualified models efficiently. The mean of the qualified models is employed as a history-matched facies probability map in the next iteration of static models. Also, the most plausible TI is determined among TI candidates by rejecting other TIs during the iteration. The posterior models of the proposed method outperform updated models of ensemble Kalman filter(EnKF) and ensemble smoother(ES) because they describe the true facies connectivity with bimodal distribution and predict oil and water production with a reasonable range of uncertainty. In terms of simulation time, it requires 30 times of forward simulation in history matching, while the EnKF and ES need 9000 times and 200 times, respectively.

An FPGA-Based Pulse Pile-up Rejection Technique for Photon Counting Imaging Detectors

A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. Tile method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are introduced in detail. The photon counting imaging detector comprises a micro-channel plate （MCP） stack, and a wedge and strip anode （WSA）. The resolution mask pattern in front of the MCP can be reconstructed after data processing in the FPGA. For high count rates, the rejection design can effectively reduce the impact of the pulse pile-up on the image. The resolution can reach up to 140μm. The pulse pile-up rejection design can also be applied to high-energy physics and particle detection.

One-Branch Zero-IF Wireless Receiver Topology with Multiphase Local Oscillator

This paper proposes a one-branch zero-IF receiver topology, which samples the I and Q signals of the modulated RF carrier with one signal path by means of a multiphase local oscillator. The suggested one-branch re- ceiver works without matching problem, and it is also capable of cancelling out the flicker noise and DC-offset when the local oscillator is configured to the four-phase mode. The one-branch receiver saves much area and power com- pared with the traditional two-branch ones. All of the advantages above make the one-branch receiver topology a promising architectural candidate for low-power and low-cost RF CMOS receiver designs. Keywords： RF CMOS; zero-IF; flicker noise; image rejection; low-power; IQ matching

A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

The design,implementation,and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters（PPF） are presented.The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion.Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band.Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip,the mixer exhibits a high image rejection ratio（IRR） of 58 dB,a power consumption of 11 mW,and a 1-dB gain compression point of-15 dBm.

An anti-image interference quadrature IF architecture for satellite receivers

Since Global Navigation Satellite System（GNSS） signals span a wide range of frequency, wireless signals coming from other communication systems may be aliased and appear as image interference. In quadrature intermediate frequency（IF） receivers, image aliasing due to in-phase and quadrature（I/Q） channel mismatches is always a big problem. I/Q mismatches occur because of gain and phase imbalances between quadrature mixers and capacitor mismatches in analog-to-digital converters（ADC）. As a result, the dynamic range and performance of a receiver are severely degraded. In this paper, several popular receiver architectures are summarized and the image aliasing problem is investigated in detail. Based on this analysis, a low-IF architecture is proposed for a single-chip solution and a novel and feasible anti-image algorithm is investigated. With this anti-image digital processing, the image reject ratio（IRR） can reach approximately above50 dB, which relaxes image rejection specific in front-end circuit designs and allows cheap and highly flexible analog front-end solutions. Simulation and experimental data show that the antiimage algorithm can work effectively, robustly, and steadily.

Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer

A 19 mW highly integrated GPS receiver with a ΣΔ fractional-N synthesizer is presented in this paper.Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design.A high linearity low noise amplifier(LNA) is integrated into the chip.The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor(CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package.The chip consumes 19 mW(LNA1 excluded) and the LNA1 6.3 mW.Measured performances are:noise figure<2 dB, channel gain=108 dB(LNA1 included), image rejection>36 dB, and-108 dBc/Hz @ 1 MHz phase noise offset from the carrier.The carrier noise ratio(C/N) can reach 41 dB at an input power of-130 dBm.The chip operates over a temperature range of-40, 120 °C and ±5% tolerance over the CMOS technology process.