Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. ...Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.展开更多
The ground-state energy level （GEL） and electron distribution of GaAs pseudomorphic high-electron-mobility transistors （PHEMTs） are analyzed by a self-consistent solution to the Schrodinger-Poisson equations. The ...The ground-state energy level （GEL） and electron distribution of GaAs pseudomorphic high-electron-mobility transistors （PHEMTs） are analyzed by a self-consistent solution to the Schrodinger-Poisson equations. The indium composition and thickness of the InGaAs channel are optimized according to the GEL position. The GEL position is not in direct proportion to 1/d^2 （d is the channel thickness） by considering the influence of electron distribution in the InGaAs channel. Indium composition 0.22 and channel thickness 9 nm are obtained by considering the mismatch between InGaAs and AlGaAs. Several PHEMT samples are grown according to the theoretical results and mobility 6300 cm^2 /V.s is achieved.展开更多
基金Supported by the National Science and Technology Major Project of China under Grant No 2011ZX02708-003the National Natural Science Foundation of China under Grant No 61504165the Opening Project of Key Laboratory of Microelectronics Devices and Integrated Technology of Institute of Microelectronics of Chinese Academy of Sciences
文摘Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.
文摘The ground-state energy level （GEL） and electron distribution of GaAs pseudomorphic high-electron-mobility transistors （PHEMTs） are analyzed by a self-consistent solution to the Schrodinger-Poisson equations. The indium composition and thickness of the InGaAs channel are optimized according to the GEL position. The GEL position is not in direct proportion to 1/d^2 （d is the channel thickness） by considering the influence of electron distribution in the InGaAs channel. Indium composition 0.22 and channel thickness 9 nm are obtained by considering the mismatch between InGaAs and AlGaAs. Several PHEMT samples are grown according to the theoretical results and mobility 6300 cm^2 /V.s is achieved.
