Photoelectric synaptic devices could emulate synaptic behaviors utilizing photoelectric effects and offer promising prospects with their high-speed operation and low crosstalk. In this study, we introduced a novel InG...Photoelectric synaptic devices could emulate synaptic behaviors utilizing photoelectric effects and offer promising prospects with their high-speed operation and low crosstalk. In this study, we introduced a novel InGaZnO-based photoelectric memristor. Under both electrical and optical stimulation, the device successfully emulated synaptic characteristics including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), long-term potentiation (LTP), and long-term depression (LTD). Furthermore, we demonstrated the practical application of our synaptic devices through the recognition of handwritten digits. The devices have successfully shown their ability to modulate synaptic weights effectively through light pulse stimulation, resulting in a recognition accuracy of up to 93.4%. The results illustrated the potential of IGZO-based memristors in neuromorphic computing, particularly their ability to simulate synaptic functionalities and contribute to image recognition tasks.展开更多
采用射频磁控溅射法在不同氧气流量条件下制备了非晶In Ga Zn O(a-IGZO)薄膜。利用霍尔效应,X射线光电子能谱(XPS)和光透过率谱研究了氧气流量对a-IGZO薄膜性能影响的规律。研究表明a-IGZO薄膜呈现n型半导体特性。当氧气流量为0.5 m L/...采用射频磁控溅射法在不同氧气流量条件下制备了非晶In Ga Zn O(a-IGZO)薄膜。利用霍尔效应,X射线光电子能谱(XPS)和光透过率谱研究了氧气流量对a-IGZO薄膜性能影响的规律。研究表明a-IGZO薄膜呈现n型半导体特性。当氧气流量为0.5 m L/min时薄膜电子迁移率达到最大12 cm2/Vs。当氧气流量大于1 m L/min时,薄膜呈现出半绝缘电导特性。XPS揭示了a-IGZO薄膜中In,Ga,Zn元素均以In3+,Ga3+及Zn2+价态存在,氧气流量分别为0和4 m L/min的a-IGZO薄膜的O 1s高分辨率XPS图谱表明低氧气流量a-IGZO薄膜中存在与氧空位相关的氧晶格元素O 1s峰而高氧气流量样品中没有显示此峰,表明生长过程中增加氧气流量降低了a-IGZO中氧空位缺陷浓度。此外,a-IGZO薄膜在可见光范围内的光透过率随氧气流量的增加而提高,当氧气流量为1 m L/min时a-IGZO薄膜平均透过率达到80%,光学禁带宽度为3.37 e V,为实现高性能透明a-IGZO-TFT器件奠定基础。展开更多
Dual-active-layer(DAL)amorphous InGaZnO(IGZO)thin-film transistors(TFTs)are fabricated at low temperature without post-annealing.A bottom low-resistance(low-R)IGZO layer and a top high-resistance(high-R)IGZO layer con...Dual-active-layer(DAL)amorphous InGaZnO(IGZO)thin-film transistors(TFTs)are fabricated at low temperature without post-annealing.A bottom low-resistance(low-R)IGZO layer and a top high-resistance(high-R)IGZO layer constitute the DAL homojunction with smooth and high-quality interface by in situ modulation of oxygen composition.The performance of the DAL TFT is significantly improved when compared to that of a single-active-layer TFT.A detailed investigation was carried out regarding the effects of the thickness of both layers on the electrical properties and gate bias stress stabilities.It is found that the low-R layer improves the mobility,ON/OFF ratio,threshold voltage and hysteresis voltage by passivating the defects and providing a smooth interface.The high-R IGZO layer has a great impact on the hysteresis,which changes from clockwise to counterclockwise.The best TFT shows a mobility of 5.41 cm^2/V·s,a subthreshold swing of 95.0 mV/dec,an ON/OFF ratio of 6.70×10^7,a threshold voltage of 0.24 V,and a hysteresis voltage of 0.13 V.The value of threshold voltage shifts under positive gate bias stress decreases when increasing the thickness of both layers.展开更多
Self-heating effect in amorphous InGaZnO thin-film transistors remains a critical issue that degrades device performance and stability, hindering their wider applications. In this work, pulsed current–voltage analysi...Self-heating effect in amorphous InGaZnO thin-film transistors remains a critical issue that degrades device performance and stability, hindering their wider applications. In this work, pulsed current–voltage analysis has been applied to explore the physics origin of self-heating induced degradation, where Joule heat is shortly accumulated by drain current and dissipated in repeated time cycles as a function of gate bias. Enhanced positive threshold voltage shift is observed at reduced heat dissipation time, higher drain current, and increased gate width. A physical picture of Joule heating assisted charge trapping process has been proposed and then verified with pulsed negative gate bias stressing scheme, which could evidently counteract the self-heating effect through the electric-field assisted detrapping process. As a result, this pulsed gate bias scheme with negative quiescent voltage could be used as a possible way to actively suppress self-heating related device degradation.展开更多
An analytical drain current model on the basis of the surface potential is proposed for indium-gallium zinc oxide(InGaZnO)thin-film transistors(TFTs)with an independent dual-gate(IDG)structure.For a unified expression...An analytical drain current model on the basis of the surface potential is proposed for indium-gallium zinc oxide(InGaZnO)thin-film transistors(TFTs)with an independent dual-gate(IDG)structure.For a unified expression of carriers’distribution for the sub-threshold region and the conduction region,the concept of equivalent flat-band voltage and the Lambert W function are introduced to solve the Poisson equation,and to derive the potential distribution of the active layer.In addition,the regional integration approach is used to develop a compact analytical current-voltage model.Although only two fitting parameters are required,a good agreement is obtained between the calculated results by the proposed model and the simulation results by TCAD.The proposed current-voltage model is then implemented by using Verilog-A for SPICE simulations of a dual-gate InGaZnO TFT integrated inverter circuit.展开更多
针对异步对称双栅结构的氧化铟镓锌(InGaZnO)薄膜晶体管(thin film transistors,TFTs),求解泊松方程,并根据载流子在亚阈区、导通区的不同分布特点,在亚阈区引入等效平带电压的概念,在导通区运用Lambert W函数近似,建立异步对称双栅InGa...针对异步对称双栅结构的氧化铟镓锌(InGaZnO)薄膜晶体管(thin film transistors,TFTs),求解泊松方程,并根据载流子在亚阈区、导通区的不同分布特点,在亚阈区引入等效平带电压的概念,在导通区运用Lambert W函数近似,建立异步对称双栅InGaZnO TFT表面电势解析模型。该模型的拟合参数只有2个,能够较好地反映介电层厚度、沟道电压等参数对电势的影响。基于所建模型及TCAD分析,研究InGaZnO层厚度、栅介质层厚度以及缺陷态密度等物理量对独立栅控双栅晶体管表面电势的影响。研究结果表明:在亚阈区,表面电势随着底栅电压增大呈近似线性增大,且在顶栅电压调制作用下平移;在导通区,表面电势随着底栅电压的增加逐步饱和,且电势值与顶栅调制电压作用相关度小。表面电势的解析模型与TCAD数值计算结果对比,具有较高的吻合度;在不同缺陷态密度分布情况下,电势模型的计算值与TCAD分析值相对误差均小于10%。本研究成果有利于了解双栅InGaZnO TFT的导通机制,可用于InGaZnO TFT的器件建模及相关集成电路设计。展开更多
基金supported by the National Key Research and Development Program of China (2021YFA1202600)the NSFC (92064009, 22175042)+3 种基金the Science and Technology Commission of Shanghai Municipality (22501100900)the China Postdoctoral Science Foundation (2022TQ0068, 2023M740644)the Shanghai Sailing Program (23YF1402200, 23YF1402400)the Qilu Young Scholar Program of Shandong University。
文摘Photoelectric synaptic devices could emulate synaptic behaviors utilizing photoelectric effects and offer promising prospects with their high-speed operation and low crosstalk. In this study, we introduced a novel InGaZnO-based photoelectric memristor. Under both electrical and optical stimulation, the device successfully emulated synaptic characteristics including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), long-term potentiation (LTP), and long-term depression (LTD). Furthermore, we demonstrated the practical application of our synaptic devices through the recognition of handwritten digits. The devices have successfully shown their ability to modulate synaptic weights effectively through light pulse stimulation, resulting in a recognition accuracy of up to 93.4%. The results illustrated the potential of IGZO-based memristors in neuromorphic computing, particularly their ability to simulate synaptic functionalities and contribute to image recognition tasks.
文摘采用射频磁控溅射法在不同氧气流量条件下制备了非晶In Ga Zn O(a-IGZO)薄膜。利用霍尔效应,X射线光电子能谱(XPS)和光透过率谱研究了氧气流量对a-IGZO薄膜性能影响的规律。研究表明a-IGZO薄膜呈现n型半导体特性。当氧气流量为0.5 m L/min时薄膜电子迁移率达到最大12 cm2/Vs。当氧气流量大于1 m L/min时,薄膜呈现出半绝缘电导特性。XPS揭示了a-IGZO薄膜中In,Ga,Zn元素均以In3+,Ga3+及Zn2+价态存在,氧气流量分别为0和4 m L/min的a-IGZO薄膜的O 1s高分辨率XPS图谱表明低氧气流量a-IGZO薄膜中存在与氧空位相关的氧晶格元素O 1s峰而高氧气流量样品中没有显示此峰,表明生长过程中增加氧气流量降低了a-IGZO中氧空位缺陷浓度。此外,a-IGZO薄膜在可见光范围内的光透过率随氧气流量的增加而提高,当氧气流量为1 m L/min时a-IGZO薄膜平均透过率达到80%,光学禁带宽度为3.37 e V,为实现高性能透明a-IGZO-TFT器件奠定基础。
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11674405,61874139,and 11675280)
文摘Dual-active-layer(DAL)amorphous InGaZnO(IGZO)thin-film transistors(TFTs)are fabricated at low temperature without post-annealing.A bottom low-resistance(low-R)IGZO layer and a top high-resistance(high-R)IGZO layer constitute the DAL homojunction with smooth and high-quality interface by in situ modulation of oxygen composition.The performance of the DAL TFT is significantly improved when compared to that of a single-active-layer TFT.A detailed investigation was carried out regarding the effects of the thickness of both layers on the electrical properties and gate bias stress stabilities.It is found that the low-R layer improves the mobility,ON/OFF ratio,threshold voltage and hysteresis voltage by passivating the defects and providing a smooth interface.The high-R IGZO layer has a great impact on the hysteresis,which changes from clockwise to counterclockwise.The best TFT shows a mobility of 5.41 cm^2/V·s,a subthreshold swing of 95.0 mV/dec,an ON/OFF ratio of 6.70×10^7,a threshold voltage of 0.24 V,and a hysteresis voltage of 0.13 V.The value of threshold voltage shifts under positive gate bias stress decreases when increasing the thickness of both layers.
基金Project supported by the National Key R&D Program of China(Grant No.2016YFB0400100)the National Natural Science Foundation of China(Grant No.91850112)+3 种基金the Natural Science Foundation of Jiangsu Province,China(Grant No.BK20161401)the Priority Academic Program Development of Jiangsu Higher Education Institutions,Chinathe Science and Technology Project of State Grid Corporation of China(Grant No.SGSDDK00KJJS1600071)the Fundamental Research Funds for the Central Universities,China(Grant No.14380098)
文摘Self-heating effect in amorphous InGaZnO thin-film transistors remains a critical issue that degrades device performance and stability, hindering their wider applications. In this work, pulsed current–voltage analysis has been applied to explore the physics origin of self-heating induced degradation, where Joule heat is shortly accumulated by drain current and dissipated in repeated time cycles as a function of gate bias. Enhanced positive threshold voltage shift is observed at reduced heat dissipation time, higher drain current, and increased gate width. A physical picture of Joule heating assisted charge trapping process has been proposed and then verified with pulsed negative gate bias stressing scheme, which could evidently counteract the self-heating effect through the electric-field assisted detrapping process. As a result, this pulsed gate bias scheme with negative quiescent voltage could be used as a possible way to actively suppress self-heating related device degradation.
基金Project supported by the National Key Research and Development Program of China(Grant No.2017YFA0204600)the Fundamental Research Funds for the Central Universities of Central South University,China(Grant No.2019zzts424)。
文摘An analytical drain current model on the basis of the surface potential is proposed for indium-gallium zinc oxide(InGaZnO)thin-film transistors(TFTs)with an independent dual-gate(IDG)structure.For a unified expression of carriers’distribution for the sub-threshold region and the conduction region,the concept of equivalent flat-band voltage and the Lambert W function are introduced to solve the Poisson equation,and to derive the potential distribution of the active layer.In addition,the regional integration approach is used to develop a compact analytical current-voltage model.Although only two fitting parameters are required,a good agreement is obtained between the calculated results by the proposed model and the simulation results by TCAD.The proposed current-voltage model is then implemented by using Verilog-A for SPICE simulations of a dual-gate InGaZnO TFT integrated inverter circuit.
